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| Cover 88F6281 Integrated Controller Hardware Specifications Doc. No. MV-S104859-U0, Rev. E December 2, 2008, Preliminary Marvell. Moving Forward Faster Document Classification: Proprietary Information 88F6281 Hardware Specifications Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S104859-U0 Rev. E Page 2 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary 88F6281 Integrated Controller Hardware Specifications PRODUCT OVERVIEW The Marvell(R) 88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell proprietary, ARMv5TE-compliant, high-speed SheevaTM CPU core. The CPU core integrates a 256 KB L2 cache. Processor SheevaTM CPU Core JTAG Interface High Speed I/0 L2 Cache 256 KB PCI Express SATA PCI Express x1 16 KB-I, 16 KB-D Up to 1.5 GHz Dual SATA ports Memory External DDR 800 MHz DDR SDRAM Controller USB 2.0 USB 2.0 port Media Interfaces Internal Bus Security Engine AES/DES/ 3DES SHA-1/MD5 MPEG TS Audio MPEG2-TS I2S / S/PDIF XOR Engine 4 XOR/DMA channels Misc FXS / FXO TDM UART x2 GPIO, TWSI Slow Bus Gigabit Ethernet IEEE 1588AVB support GE GE SPI, NAND, SDIO Flash, SDIO 88F6281 Functional Block Diagram Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 3 88F6281 Hardware Specifications FEATURES The 88F6281 includes: * High-performance CPU core, running at up to 1.5 GHz, with integrated, four-way, set-associative L1 16-KB I-cache/16-KB D-cache and unified, 256-KB, four-way, set-associative L2 cache * High-bandwidth dual-port DDR2 memory interface (16-bit DDR2 SDRAM @ up to 800 MHz data rate) * PCI Express (x1) port with integrated PHY * Two Gigabit Ethernet (10/100/1000 Mbps) MACs * USB 2.0 port with integrated PHY * Two SATA 2.0 ports with integrated 3 Gbps SATA II PHY * Security Cryptographic engine * S/PDIF (Sony/Philips Digital Interconnect Format) / I2S (Integrated Interchip Sound) Audio in/out interface SD/SDIO/MMC interface TDM SLIC/SLAC Codec interface Two XOR engines, each containing two XOR/DMA channels (a total of four XOR/DMA channels) MPEG Transport Stream (TS) interface SPI port with SPI flash boot support 8-bit NAND flash interface with boot support Two 16550 compatible UART interfaces TWSI port 50 multi-purpose pins Internal Real Time Clock (RTC) Interrupt controller Timers 128-bit eFuse (one-time programmable memory) * DDR SDRAM with a clock ratio of 1:N and 2:N * * * * * * * * * * between the DDR SDRAM and the CPU core, respectively SSTL 1.8V I/Os Auto calibration of I/Os output impedance Supports four DRAM chip selects Supports all DDR devices densities up to 2 Gb Supports up to 32 open pages (page per bank) Up to 2 GB total address space Supports on-board DDR designs (no DIMM support) Supports 2T mode, to enable high-frequency operation under heavy load configuration Supports DRAM bank interleaving Supports up to a 128-byte burst per single memory access * * * * * * * * * * * * * PCI Express interface (x1) * PCI Express Base 1.1 compatible * Integrated low-power SERDES PHY, based on SheevaTM CPU core * Up to 1.5 GHz * 32-bit and 16-bit RISC architecture * Compliant with v5TE architecture, as published in the ARM Architect Reference Manual, Second Edition * Includes MMU to support virtual memory features * 256-KB, four-way, set-associative L2 unified cache * 16-KB, four-way, set-associative I-cache * 16-KB, four-way, set-associative D-cache * 64-bit internal data bus * Branch Prediction Unit * Supports JTAG/ARM ICE * Supports both Big and Little Endian modes DDR2 SDRAM controller * 16-bit interface * Up to 400 MHz clock frequency (800 MHz data rate) * * * * * * * * * * * * proven Marvell(R) SERDES technology Serves as a Root Complex or an Endpoint port x1 link width 2.5 Gbps data rate Lane polarity reversal support Maximum payload size of 128 bytes Single Virtual Channel (VC-0) Replay buffer support Extended PCI Express configuration space Advanced Error Reporting (AER) support Power management: L0s and software L1 support Interrupt emulation message support Error message support PCI Express master specific features * Single outstanding read transaction * Maximum read request of up to 128 bytes * Maximum write request of up to 128 bytes * Up to four outstanding read transactions in Endpoint mode PCI Express target specific features * Supports up to eight read request transactions * Maximum read request size of 4 KB * Maximum write request of 128 bytes * Supports PCI Express access to all of the controller's internal registers Two Integrated GbE (10/100/1000) MAC ports * Supports 10/100/1000 Mbps * Dedicated DMA for data movement between memory and port Doc. No. MV-S104859-U0 Rev. E Page 4 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Features * Priority queuing on receive based on Destination Address (DA), VLAN Tag, and IP TOS * Layer 2/3/4 frame encapsulation detection * TCP/IP checksum on receive and transmit * Supports proprietary 200 Mbps Marvell MII (MMII) interface * Supports four modes: - Port 0 RGMII, Port 1 RGMII - Port 0 RGMII, Port 1 MII/MMII - Port 0 MII/MMII, port 1 RGMII - Port 0 GMII, Port 1 N/A *DA filtering Precise Timing Protocol (PTP) * Supports precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE 802.1AS draft standards * Supports Flexible Time Application interface to distribute PTP clock and time to other devices in the system * Optionally accepts an external clock input for time stamping Audio Video Bridging networks * Supports IEEE 802.1Qav draft Audio Video Bridging networks * Supports time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects--suitable for audio/video applications * Supports Egress Jitter Pacer for AVB-Class A and AVB-Class B traffic and strict priority for legacy traffic queues USB 2.0 port * Serves as a peripheral or host * USB 2.0 compliant * Integrated USB 2.0 PHY * Enhanced Host Controller Interface (EHCI) compatible as a host * As a host, supports direct connection to all peripheral types (LS, FS, HS) * As a peripheral, connects to all host types (HS, FS) and hubs * Up to four independent endpoints, supporting control, interrupt, bulk, and isochronous data transfers * Dedicated DMA for data movement between memory and port Two Integrated Marvell 3 Gbps (Gen2i) SATA PHYs * Compliant with SATA II Phase 1 specifications - Supports SATA II Native Command Queuing (NCQ), up to 128 outstanding commands per port - Fully supports first party DMA (FPDMA) - Backwards compatible with SATA I devices * Supports SATA II Phase 2 advanced features - 3 Gbps (Gen2i) SATA II speed - Port Multiplier (PM)--Performs FIS-based switching, as defined in SATA working group PM definition - Port Selector (PS)--Issues the protocol-based Out-Of-Band (OOB) sequence for selecting the active host port * Supports device 48-bit addressing * Supports ATA Tag Command Queuing SATA II Host Controller * Enhanced-DMA (EDMA) for the SATA ports * Automatic command execution, without host intervention * Command queuing support, for up to 32 outstanding commands * Separate SATA request/response queues * 64-bit addressing support for descriptors and data buffers in system memory * Read ahead * Advanced interrupt coalescing * Target mode operation--supports attaching two 88F6281 controllers through their Serial-ATA ports, enabling data communication between the 88F6281 controllers * Advanced drive diagnostics via the ATA SMART command Cryptographic engine * Hardware implementation on encryption and authentication engines, to boost packet processing speed * Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the DDR memory * Implements AES, DES, and 3DES encryption algorithms * Implements SHA1 and MD5 authentication algorithms S/PDIF / I2S Audio In/Out interface * Either S/PDIF or I2S inputs can be active at one time * Both S/PDIF and I2S outputs can be simultaneously active, transferring the same PCM data S/PDIF-specific features * Compliant with 60958-1, 60958-3, and IEC61937 specifications * Sample rates of 44.1/48/96 kHz * 16/20/24-bit depths Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 5 88F6281 Hardware Specifications I2S-specific features * Sample rates of 44.1/48/96 kHz * I2S input and I2S output operate at the same sample rate * 16/24-bit depths * I2S in and I2S out support independent bit depths (16 bit/24 bit) MPEG Transport Stream (TS) interface * ISO/IEC 13818-1 standard compliant * Supports any one of the following modes: - Parallel (8 bit) input - Parallel output - Two independent serial interfaces * Data rate up to 80 Mbps Two UART Interfaces * 16550 UART compatible * Two pins for transmit and receive operations * Two pins for modem control functions Two-Wire Serial Interface (TWSI) * General purpose TWSI master/slave port * Can also be used for serial ROM initialization 50 dedicated Multi-Purpose Pins (MPPs) for peripheral functions and general purpose I/O * Each pin can be configured independently. * GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts. * Only two of the following multiplexed interfaces may be configured simultaneously: - Audio - TS - TDM - GbE Port 0 in GMII mode or GbE Port 1 Interrupt Controller Maskable interrupts to CPU core (and PCI Express for a PCI Express endpoint) Two general purpose 32-bit timers/counters Internal architecture * Mbus-L bus for high-performance, low-latency CPU core to DDR SDRAM connectivity * Advanced Mbus architecture * Dual port DDR SDRAM controller connectivity to both CPU and Mbus Bootable from * SPI flash * SATA device * NAND flash * PCI Express * UART (for debug purpose) 288-pin HSBGA package, 19 x 19 mm, 1 mm ball pitch * Supports plain I2S, right-justified and left-justified formats SD/SDIO/MMC host interface * 1-bit/4-bit SDmem, SDIO, and MMC cards * Up to 50 MHz * Hardware generate/check CRC, on all command and data transactions on the card bus TDM SLIC/SLAC Codec interface * Generic interface to standard SLIC/SLAC codec devices * Compatible with standard PCM highway formats * TDM protocol support for two channels, up to 128 time slots * Dedicated SPI interface for codec management * Integrated DMA to transfer voice data to/from memory buffer Two XOR engines and DMA * Two XOR/DMA channels per XOR engine (for a total of four XOR/DMA channels) * Chaining via linked-lists of descriptors * Moves data from source interface to destination interface * Supports increment or hold on both Source and Destination Addresses * Supports XOR operation, on up to eight source blocks--useful for RAID applications * Supports iSCSI CRC-32 calculation NAND flash controller * 8-bit NAND flash interface * Glueless interface to CE Care and CE Don't Care NAND flash devices * Boot support Serial Peripheral Interface (SPI) controller * Up to 50 MHz clock * Supports direct boot from external SPI serial flash memory Doc. No. MV-S104859-U0 Rev. E Page 6 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Features SATA Port Multiplier HDD PCI Express Mini Card Wi-Fi On Board DDR2 x16 SPI Flash (op.) SD Card 88F6281 USB Host x8 TDM NAND Flash Audio A/D - D/A GbE PHY FXS FXO Usage Model Example: VoIP Gateway Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 7 88F6281 Hardware Specifications Table of Contents Product Overview ....................................................................................................................................... 3 Features....................................................................................................................................................... 4 Preface.......................................................................................................................................................15 About this Document .......................................................................................................................................15 Related Documentation...................................................................................................................................15 Document Conventions ...................................................................................................................................16 1 1.1 1.2 1.3 Pin and Signal Descriptions ....................................................................................................... 17 Pin Logic .........................................................................................................................................................18 Pin Descriptions ..............................................................................................................................................19 Internal Pull-up and Pull-down Pins ................................................................................................................48 2 3 4 4.1 4.2 4.3 Unused Interface Strapping........................................................................................................ 49 88F6281 Pin Map and Pin List .................................................................................................... 50 Pin Multiplexing ........................................................................................................................... 51 Multi-Purpose Pins Functional Summary ........................................................................................................51 Gigabit Ethernet (GbE) Pins Multiplexing on MPP ..........................................................................................57 TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59 5 5.1 Clocking ....................................................................................................................................... 60 Spread Spectrum Clock Generator (SSCG)....................................................................................................62 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 System Power Up/Down and Reset Settings ............................................................................ 63 Power-Up/Down Sequence Requirements......................................................................................................63 Hardware Reset ..............................................................................................................................................64 PCI Express Reset ..........................................................................................................................................66 SheevaTM CPU TAP Controller Reset..............................................................................................................66 Pins Sample Configuration..............................................................................................................................66 Serial ROM Initialization ..................................................................................................................................70 Boot Sequence................................................................................................................................................71 7 7.1 7.2 7.3 7.4 7.5 JTAG Interface ............................................................................................................................. 73 TAP Controller.................................................................................................................................................73 Instruction Register .........................................................................................................................................73 Bypass Register ..............................................................................................................................................74 JTAG Scan Chain ...........................................................................................................................................74 ID Register ......................................................................................................................................................74 Doc. No. MV-S104859-U0 Rev. E Page 8 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Table of Contents 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Electrical Specifications (Preliminary) ...................................................................................... 75 Absolute Maximum Ratings ............................................................................................................................75 Recommended Operating Conditions .............................................................................................................77 Thermal Power Dissipation .............................................................................................................................79 Current Consumption ......................................................................................................................................80 DC Electrical Specifications ............................................................................................................................81 AC Electrical Specifications ............................................................................................................................86 Differential Interface Electrical Characteristics..............................................................................................118 9 10 11 11.1 11.2 Thermal Data (Preliminary) .......................................................................................................129 Package ......................................................................................................................................130 Part Order Numbering/Package Marking ................................................................................132 Part Order Numbering ...................................................................................................................................132 Package Marking ..........................................................................................................................................133 A Revision History ........................................................................................................................134 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 9 88F6281 Hardware Specifications List of Tables 1 Pin and Signal Descriptions ............................................................................................................ 17 Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Pin Functions and Assignments Table Key ......................................................................................19 Interface Pin Prefix Codes ................................................................................................................19 Power Pin Assignments ....................................................................................................................21 Miscellaneous Pin Assignments .......................................................................................................23 DDR SDRAM Interface Pin Assignments .........................................................................................24 PCI Express Interface Pin Assignments ...........................................................................................26 SATA Port Interface Pin Assignment ................................................................................................27 Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28 Serial Management Interface (SMI) Pin Assignments ......................................................................32 USB 2.0 Interface Pin Assignments..................................................................................................33 JTAG Pin Assignment.......................................................................................................................34 RTC Interface Pin Assignments........................................................................................................35 NAND Flash Interface Pin Assignment .............................................................................................36 MPP Interface Pin Assignment .........................................................................................................37 Two-Wire Serial Interface (TWSI) Interface Pin Assignment ............................................................38 UART Port 0/1 Interface Pin Assignment .........................................................................................39 Audio (S/PDIF / I2S) Interface Signal Assignment ............................................................................40 Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................41 Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42 Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43 Transport Stream (TS) Interface Signal Assignment ........................................................................45 Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47 Internal Pull-up and Pull-down Pins ..................................................................................................48 2 3 4 Unused Interface Strapping............................................................................................................. 49 Table 24: Unused Interface Strapping ..............................................................................................................49 88F6281 Pin Map and Pin List ......................................................................................................... 50 Pin Multiplexing ................................................................................................................................ 51 Table 25: Table 26: Table 27: Table 28: MPP Functionality .............................................................................................................................52 MPP Function Summary ...................................................................................................................53 Ethernet Ports Pins Multiplexing .......................................................................................................57 TS Port Pin Multiplexing .................................................................................................................59 5 Clocking............................................................................................................................................. 60 Table 29: Table 30: 88F6281Clocks.................................................................................................................................60 Supported Clock Combinations ........................................................................................................61 6 System Power Up/Down and Reset Settings ................................................................................. 63 Table 31: Table 32: I/O and Core Voltages ......................................................................................................................63 Reset Configuration ..........................................................................................................................67 Doc. No. MV-S104859-U0 Rev. E Page 10 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary List of Tables 7 JTAG Interface .................................................................................................................................. 73 Table 33: Table 34: Supported JTAG Instructions............................................................................................................73 IDCODE Register Map .....................................................................................................................74 8 Electrical Specifications (Preliminary) ........................................................................................... 75 Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Absolute Maximum Ratings ..............................................................................................................75 Recommended Operating Conditions...............................................................................................77 Thermal Power Dissipation ...............................................................................................................79 Current Consumption........................................................................................................................80 General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................81 RGMII 1.8V Interface (CMOS) DC Electrical Specifications .............................................................82 SDRAM DDR2 Interface DC Electrical Specifications ......................................................................83 TWSI Interface 3.3V DC Electrical Specifications.............................................................................84 SPI Interface 3.3V DC Electrical Specifications................................................................................84 TDM Interface 3.3V DC Electrical Specifications..............................................................................85 Reference Clock AC Timing Specifications ......................................................................................86 SDRAM DDR2 Interface AC Timing Table .......................................................................................88 SDRAM DDR2 Interface Address Timing Table ...............................................................................89 SDRAM DDR2 Clock Specifications .................................................................................................90 RGMII 10/100/1000 AC Timing Table at 1.8V ..................................................................................93 RGMII 10/100 AC Timing Table at 3.3V ...........................................................................................93 GMII AC Timing Table ......................................................................................................................95 MII/MMII MAC Mode AC Timing Table .............................................................................................97 SMI Master Mode AC Timing Table..................................................................................................99 JTAG Interface AC Timing Table ....................................................................................................101 TWSI Master AC Timing Table .......................................................................................................103 TWSI Slave AC Timing Table .........................................................................................................103 S/PDIF AC Timing Table ................................................................................................................105 Inter-IC Sound (I2S) AC Timing Table ............................................................................................107 TDM Interface AC Timing Table .....................................................................................................109 SPI (Master Mode) AC Timing Table ..............................................................................................111 SDIO Host in High Speed Mode AC Timing Table .........................................................................113 Transport Stream Output Interface AC Timing Table ....................................................................115 Transport Stream Input Interface AC Timing Table ........................................................................115 PCI Express Interface Differential Reference Clock Characteristics ..............................................118 PCI Express Interface Spread Spectrum Requirements.................................................................119 PCI Express Interface Driver and Receiver Characteristics ...........................................................120 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics ...............................................123 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................124 USB Low Speed Driver and Receiver Characteristics ....................................................................125 USB Full Speed Driver and Receiver Characteristics.....................................................................126 USB High Speed Driver and Receiver Characteristics ...................................................................127 9 Thermal Data (Preliminary) ............................................................................................................129 Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) .............................129 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 11 88F6281 Hardware Specifications 10 11 A Package ...........................................................................................................................................130 Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131 Part Order Numbering/Package Marking......................................................................................132 Table 74: 88F6281 Part Order Options ..........................................................................................................132 Revision History .............................................................................................................................134 Table 75: Revision History ..............................................................................................................................134 Doc. No. MV-S104859-U0 Rev. E Page 12 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary List of Figures List of Figures 1 Pin and Signal Descriptions ........................................................................................................... 17 Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18 2 3 4 5 6 Unused Interface Strapping............................................................................................................ 49 88F6281 Pin Map and Pin List ........................................................................................................ 50 Pin Multiplexing ............................................................................................................................... 51 Clocking............................................................................................................................................ 60 System Power Up/Down and Reset Settings ................................................................................ 63 Figure 2: Figure 3: Figure 4: Power-Up Sequence Example..........................................................................................................64 Serial ROM Data Structure ...............................................................................................................70 Serial ROM Read Example...............................................................................................................71 7 8 JTAG Interface ................................................................................................................................. 73 Electrical Specifications (Preliminary) .......................................................................................... 75 Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: SDRAM DDR2 Interface Test Circuit ................................................................................................91 SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91 SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................92 SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................92 RGMII Test Circuit ............................................................................................................................94 RGMII AC Timing Diagram ...............................................................................................................94 GMII Test Circuit ...............................................................................................................................95 GMII Output AC Timing Diagram ......................................................................................................96 GMII Input AC Timing Diagram.........................................................................................................96 MII/MMII MAC Mode Test Circuit......................................................................................................97 MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97 MII/MMII MAC Mode Input AC Timing Diagram................................................................................98 MDIO Master Mode Test Circuit .......................................................................................................99 MDC Master Mode Test Circuit ......................................................................................................100 SMI Master Mode Output AC Timing Diagram ...............................................................................100 SMI Master Mode Input AC Timing Diagram ..................................................................................100 JTAG Interface Test Circuit ............................................................................................................101 JTAG Interface Output Delay AC Timing Diagram .........................................................................102 JTAG Interface Input AC Timing Diagram ......................................................................................102 TWSI Test Circuit............................................................................................................................104 TWSI Output Delay AC Timing Diagram.........................................................................................104 TWSI Input AC Timing Diagram .....................................................................................................104 S/PDIF Test Circuit .........................................................................................................................106 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 13 88F6281 Hardware Specifications Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107 Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108 Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108 TDM Interface Test Circuit ..............................................................................................................109 TDM Interface Output Delay AC Timing Diagram...........................................................................110 TDM Interface Input Delay AC Timing Diagram..............................................................................110 SPI (Master Mode) Test Circuit ......................................................................................................111 SPI (Master Mode) Output AC Timing Diagram .............................................................................112 SPI (Master Mode) Input AC Timing Diagram ................................................................................112 Secure Digital Input/Output (SDIO) Test Circuit .............................................................................113 SDIO Host in High Speed Mode Output AC Timing Diagram .........................................................114 SDIO Host in High Speed Mode Input AC Timing Diagram............................................................114 Transport Stream Interface Test Circuit..........................................................................................116 Transport Stream Output Interface AC Timing Diagram ................................................................116 Transport Stream Input Interface AC Timing Diagram ...................................................................117 PCI Express Interface Test Circuit..................................................................................................121 Low/Full Speed Data Signal Rise and Fall Time ............................................................................127 High Speed TX Eye Diagram Pattern Template .............................................................................128 High Speed RX Eye Diagram Pattern Template.............................................................................128 9 10 Thermal Data (Preliminary) ........................................................................................................... 129 Package .......................................................................................................................................... 130 Figure 47: HSBGA 288-pin Package and Dimensions ...................................................................................130 11 Part Order Numbering/Package Marking..................................................................................... 132 Figure 48: Figure 49: Sample Part Number ......................................................................................................................132 Commercial Package Marking and Pin 1 Location .........................................................................133 Doc. No. MV-S104859-U0 Rev. E Page 14 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Preface About this Document Preface About this Document This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications. This datasheet is intended to be the basic source of information for designers of new systems. In this document, the "88F6281" is often referred to as the "device". Related Documentation The following documents contain additional information related to the 88F6281: 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications, Doc No. MV-S104860-U0 SheevaTM 88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet, Doc No. MV-S104950-U0 Unified Layer 2 (L2) Cache for SheevaTM CPU Cores Addendum, Doc No. MV-S104858-U0 88F6180, 88F6190, 88F6192, and 88F6281 Functional Errata, Interface Guidelines, and Restrictions, Doc No. MV-S501157-U0 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-001 AN-63: Thermal Management for Marvell Technology Products Doc No. MV-S300281-001 AN-179: TWSI Software Guidelines for DiscoveryTM, HorizonTM, and Feroceon(R) Devices, Doc No. MV-S300754-001 AN-183: 88F5181 and 88F5281 Big Endian and Little Endian Support, Doc No. MV-S300767-001 AN-249: Configuring the Marvell(R) SATA PHY to Transmit Predefined Test Patterns, Doc No. MV-S301342-001 AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281, Doc No. MV-S301454-001 TB-227: Differences Between the 88F6190, 88F6192, and 88F6281 Stepping Z0 and A0, Doc No. MV-S105223-001 White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Doc No. MV-S700019-00 ARM Architecture Reference Manual, Second Edition PCI Express Base Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation ARC USB-HS OTG High-Speed Controller Core reference V 4.0.1 Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard) FIPS 81 (DES Modes of Operation) FIPS 180-1 (Secure Hash Standard) FIPS draft - Advanced Encryption Standard (Rijndeal) 1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the Marvell Extranet. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 15 88F6281 Hardware Specifications RFC 1321 (The MD5 Message-Digest Algorithm) RFC 1851 - The ESP Triple DES Transform RFC 2104 (HMAC: Keyed-Hashing for Message Authentication). RFC 2405 - The ESP DES-CBC Cipher Algorithm With Explicit IV IEEE standard, 802.3-2000 Clause 14 ANSI standard X3.263-1995 See the Marvell Extranet website for the latest product documentation. Document Conventions The following conventions are used in this document: Signal Range A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb). Example: DB_Addr[12:0] Active Low Signals # An n letter at the end of a signal name indicates that the signal's active state occurs when voltage is low. Example: INTn State Names State names are indicated in italic font. Example: linkfail Register Naming Conventions Register field names are indicated by angle brackets. Example: Reset Values Reset values have the following meanings: 0 = Bit clear 1 = Bit set Kb: kilobit KB: kilobyte Mb: megabit MB: megabyte Gb: gigabit GB: gigabyte Unless otherwise indicated, all numbers in this document are decimal (base 10). An 0x prefix indicates a hexadecimal number. An 0b prefix indicates a binary number. Abbreviations Numbering Conventions Doc. No. MV-S104859-U0 Rev. E Page 16 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions 1 Pin and Signal Descriptions This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 17 88F6281 Hardware Specifications 1.1 Pin Logic Figure 1: 88F6281 Pin Logic Diagram REF_CLK_XIN XOUT SYSRSTn TP ISET RESERVED MRn NC PEX_CLK_P PEX_CLK_N PEX_TX_P PEX_TX_N PEX_RX_P PEX_RX_N PEX_ISET USB_DP USB_DM VDD VDD_CPU VDDO VDD_GE_A VDD_GE_B VDD_M VSS CPU_PLL_AVDD CPU_PLL_AVSS CORE_PLL_AVDD CORE_PLL_AVSS XTAL_AVDD XTAL_AVSS PEX_AVDD SATA0_AVDD SATA1_AVDD USB_AVDD RTC_AVDD RTC_AVSS SSCG_AVDD SSCG_AVSS VHV MPP[49:0] NF_IO[7:0] NF_CLE NF_ALE NF_CEn NF_REn NF_WEn JT_CLK JT_TDI JT_TDO JT_TMS_CPU JT_TMS_CORE JT_RSTn SATA0_T_P SATA0_T_N SATA0_R_P SATA0_R_N SATA1_T_P SATA1_T_N SATA1_R_P SATA1_R_N RTC_XIN RTC_XOUT Misc. Power PCI Express USB MPP Gigabit Ethernet GE_TXCLKOUT GE_TXD[3:0] GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK GE_MDC GE_MDIO NAND Flash JTAG M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A[14:0] M_BA[2:0] M_CSn[3:0] M_DQ[15:0] M_DQS[1:0] M_DQSn[1:0] M_DM[1:0] M_ODT[1:0] M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL SDRAM SATA0/1 RTC NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock. For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional Summary, on page 51. Doc. No. MV-S104859-U0 Rev. E Page 18 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2 Pin Descriptions This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes. Table 1 Table 1: Te r m [n] Pin Functions and Assignments Table Key D e fi n it io n n - Represents the SERDES pair number Represents port number when there are more than one ports Analog Driver/Receiver or Power Supply Calibration pad type Common Mode Logic Complementary Metal-Oxide-Semiconductor Double Data Rate Ground Supply High-speed Current Steering Logic Input Input/Output Output Open Drain pin The pin allows multiple drivers simultaneously (wire-OR connection). A pull-up is required to sustain the inactive value. VDD Power Supply Stub Series Terminated Logic for 1.8V Tri-State pin n - Suffix represents an Active Low Signal Power SSTL t/s XXXn Table 2: In t e r f a c e Misc Interface Pin Prefix Codes P re fi x N/A M_ PEX_ SATA0_ SATA1_ GE_ USB_ JT_ DDR SDRAM PCI Express SATA Gigabit Ethernet USB 2.0 JTAG Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 19 88F6281 Hardware Specifications Table 2: In t e r f a c e RTC Interface Pin Prefix Codes (Continued) P re fi x RTC_ NF_ N/A TW_ UA0_ UA1_ AU_ SPI_ SD_ TDM_ PTP_ NAND Flash MPP TWSI UART Audio SPI SDIO TDM PTP Doc. No. MV-S104859-U0 Rev. E Page 20 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.1 Power Supply Pins Table 3 provides the voltage levels for the various interface pins. These do not include the analog power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables. Table 3: Power Pin Assignments I /O Pi n Ty p e Power Power Power Power D es c r ip t i o n Pin Name VDD VDD_CPU VDDO VDD_GE_A I I I I 1.0V Digital core voltage 1.1V Digital CPU voltage 3.3V I/O power for MPP[49:36],MPP[19:0] and JTAG pins 1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces 3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces I/O power for MPP[35:20] 1.8V or 3.3V I/O supply voltage for RGMII interfaces 3.3V I/O supply voltage for GMII and MII/MMII interfaces 1.8V I/O supply voltage for the DDR2 SDRAM interface VSS 1.8V analog quiet power to CPU PLL NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. CPU PLL ground 1.8V analog quiet power to Core PLL NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. Core PLL ground 1.8V quiet power supply to the internal Spread Spectrum Clock Generator Ground for the internal Spread Spectrum Clock Generator 1.8V analog quiet power to on-chip clock inverter for supporting external crystal, and on-chip current reference for SATA and USB PHYs NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. Ground for supporting external crystal, and on-chip current reference for SATA and USB PHYs I/O supply voltage for eFuse: * 2.5V for eFuse burning only * 1.0V for eFuse reading only VDD_GE_B I Power VDD_M VSS CPU_PLL_AVDD I I I Power GND Power CPU_PLL_AVSS CORE_PLL_AVDD I I GND Power CORE_PLL_AVSS SSCG_AVDD I I GND Power SSCG_AVSS XTAL_AVDD I I GND Power XTAL_AVSS I GND VHV I Power Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 21 88F6281 Hardware Specifications Table 3: Power Pin Assignments (Continued) I /O Pi n Ty p e Power D es c r ip t i o n Pin Name PEX_AVDD I PCI Express PHY quiet power supply 1.8V NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendations. SATA II port0/1 quiet 3.3V power supply NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation. USB 2.0 PHY quiet 3.3V power supply NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation. 1.5V (via battery) or 1.8V (via the board) RTC interface voltage RTC ground SATA0_AVDD SATA1_AVDD I Power USB_AVDD I Power RTC_AVDD RTC_AVSS I I Power GND Doc. No. MV-S104859-U0 Rev. E Page 22 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.2 Table 4: Miscellaneous Pin Assignment The Miscellaneous signal list contains clock and reset, test, and related signals. Miscellaneous Pin Assignments I /O Pi n Ty pe Analog P ow e r Rail XTAL_AVDD D e s c r i p t io n Pin Name REF_CLK_XIN I Reference clock input from external oscillator or input from external crystal. Used as input to core, CPU, SATA, and USB PLLs. XTAL_OUT Feedback signal to external crystal. When not used, leave this pin floating. System reset Main reset signal of the device clock. Used to reset all units to their initial state. When in the reset state, most output pins are in Tri-State. Reset request from the device to the board reset logic. This pin is multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). Optional PCI Express Endpoint card reset output This pin is multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). Analog Test Point for SATA, USB, and PCI Express interfaces For internal use. Leave this pin unconnected. Current reference for both the USB and SATA PHYs. Terminate this pin with a 6.04 k resistor, pulled down. XOUT O Analog XTAL_AVDD SYSRSTn I CMOS VDDO SYSRST_OUTn O CMOS VDDO PEX_RST_OUTn O CMOS VDDO TP O Analog ISET I Analog MRn I CMOS VDD_GE_A Active-Low, Manual Reset Input SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low, and for additional 20 ms after MRn (manual reset) de-assertion This pin is internally pulled up. Reserved for MarvellAE future usage. Leave unconnected externally. Reserved for MarvellAE future usage. Leave unconnected externally. RESERVED NC Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 23 88F6281 Hardware Specifications 1.2.3 Table 5: DDR SDRAM Interface Pin Assignments DDR SDRAM Interface Pin Assignments I /O Pi n Ty pe SSTL P ow e r Rail VDD_M D e s cr ip t i o n Pin Name M_CLKOUT M_CLKOUTn M_CKE O SDRAM Differential Clock Pair O SSTL VDD_M Driven high to enable SDRAM clock. Driven low when setting the SDRAM to Self-refresh mode. SDRAM Row Address Select Asserted to indicate an active ROW address driven on the SDRAM address lines. SDRAM Column Address Select Asserted to indicate an active column address driven on the SDRAM address lines. SDRAM Write Enable Asserted to indicate a write command to the SDRAM. SDRAM Address Driven with M_BA[2:0] during RASn and CASn cycles to generate the SDRAM address. M_RASn O SSTL VDD_M M_CASn O SSTL VDD_M M_WEn O SSTL VDD_M M_A[14:0] O SSTL VDD_M M_BA[2:0] O SSTL VDD_M Driven during M_RASn and M_CASn cycles to select one of the eight SDRAM virtual banks. NOTE: If an SDRAM device does not support the BA[2] pin, leave the M_BA[2] unconnected. SDRAM Chip Selects Asserted to select a specific SDRAM Physical bank. SDRAM Data Bus Driven during write. Driven by SDRAM during reads. SDRAM Data Strobe Driven by the 88F6281 during write. Driven by SDRAM during reads. SDRAM Data Mask Asserted by the 88F6281 to select the specific byte out of the 16-bit data to be written to the SDRAM. SDRAM On Die Termination control Driven high to connect the SDRAM on die termination. Driven low to disconnect the SDRAM's termination. NOTE: For the recommended setting, refer to the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide. M_CSn[3:0] O SSTL VDD_M M_DQ[15:0] t/s I/O SSTL VDD_M M_DQS[1:0], M_DQSn[1:0] t/s I/O SSTL VDD_M M_DM[1:0] O SSTL VDD_M M_ODT[1:0] O SSTL VDD_M Doc. No. MV-S104859-U0 Rev. E Page 24 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions Table 5: DDR SDRAM Interface Pin Assignments (Continued) I /O Pi n Ty pe SSTL P ow e r Rail VDD_M D e s cr ip t i o n Pin Name M_STARTBURST O Start Burst 88F6281 indication of starting a burst read transaction. Asserted with the first M_CASn cycle of SDRAM access. NOTE: Must be routed on board to the SDRAM, and back to the 88F6281 as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide. Start Burst Input M_START BURST_IN M_PCAL I SSTL VDD_M I Calib SDRAM interface P channel output driver calibration. Connect to VSS through a resistor. The resistor value can vary between 30-70 ohm. NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended values of the calibration resistors. SDRAM interface N channel output driver calibration. Connect to M_VDD through a resistor. The resistor value can vary between 30-70 ohm. NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended values of the calibration resistors. M_NCAL I Calib Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 25 88F6281 Hardware Specifications 1.2.4 Table 6: PCI Express Interface Pin Assignments PCI Express Interface Pin Assignments I/O P in Ty p e HCSL Power R a il PEX_AVDD D e s c r i p t io n Pin Name PEX_CLK_P/N I/O PCI Express Reference Clock 100 MHz, differential This clock can be configured as input or output according to the reset strap (see Table 32, Reset Configuration, on page 67). NOTE: For Output mode, 50-ohm, pull-down resistors are required. Transmit Lane Differential pair of PCI Express transmit data Receive Lane Differential pair of PCI Express receive data Current reference. Pull down to VSS through a 5 k resistor. See the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for the recommended resistor value. PEX_TX_P/N O CML PEX_AVDD PEX_RX_P/N I CML PEX_AVDD PEX_ISET I Analog Doc. No. MV-S104859-U0 Rev. E Page 26 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.5 Table 7: SATA Interface Pin Assignments SATA Port Interface Pin Assignment I /O Pi n Ty p e CML P ow e r R a i l D e s c r i p t io n Pin Name SATA0_T_P/N SATA1_T_P/N SATA0_R_P/N SATA1_R_P/N SATA0_PRESENTn SATA1_PRESENTn O SATA0/1_AVDD Transmit Data: Differential analog output of SATA II port0/1 Receive Data: Differential analog input of SATA II port0/1 I CML SATA0/1_AVDD O CMOS VDDO/ VDD_GE_B When this signal is asserted there is an active link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). When this signal is asserted, there is an active and used link between the SATA II port and the external device (disk). NOTE: These signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). SATA0_ACTn SATA1_ACTn O CMOS VDDO/ VDD_GE_B Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 27 88F6281 Hardware Specifications 1.2.6 Gigabit Ethernet Port Interface Pin Assignments For additional information about the Gigabit Ethernet port pin functions refer to Section 4.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 57. Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments I/O P in Ty p e Power R a il D e s c r i p t io n Pin Name Port0--Dedicated GbE Pins GE_TXCLKOUT t/s O CMOS VDD_GE_A RGMII Transmit Clock RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL. Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode. MII/MMII Transmit Clock MII/MMII transmit reference clock from PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz. CMOS VDD_GE_A RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge. MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input. GMII Transmit Data Contains the transmit data nibble outputs. GE_TXCTL t/s O CMOS VDD_GE_A RGMII Transmit Control Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is driven on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT. MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock. GMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to GE_TXCLKOUT. I t/s O GE_TXD[3:0] t/s O Doc. No. MV-S104859-U0 Rev. E Page 28 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) I/O P in Ty p e CMOS Power R a il VDD_GE_A D e s c r i p t io n Pin Name GE_RXD[3:0] I RGMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge. MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input. GMII Receive Data Contains the receive data nibble inputs. GE_RXCTL I CMOS VDD_GE_A RGMII Receive Control GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK. MII/MMII Receive Data Valid GMII Receive Data Valid. GE_RXCLK I CMOS VDD_GE_A RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at 125 MHz Port1--Multiplexed GbE Pins MPP[23:20]/ GE1[3:0] t/s O CMOS VDD_GE_B RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits [3:0] presented on the rising edge of GE_TXCLKOUT and bits [7:4] presented on the falling edge. MII/MMII Transmit Data Contains the transmit data nibble outputs that are synchronous to the transmit clock input. GMII Transmit Data Contains the transmit data nibble outputs. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 29 88F6281 Hardware Specifications Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) I/O P in Ty p e CMOS Power R a il VDD_GE_B D e s c r i p t io n Pin Name MPP[27:24]/ GE1[7:4] I RGMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input rising/falling edge. MII/MMII Receive Data Contains the receive data nibble inputs that are synchronous to GE_RXCLK input. GMII Receive Data Contains the receive data nibble inputs. MPP[28]/GE1[8] I CMOS VDD_GE_B MII/MMII Collision Detect Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock. GMII Collision Detect MPP[29]/GE1[9] I CMOS VDD_GE_B MII/MMII Transmit Clock MII/MMII transmit reference clock from PHY. Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz. t/s O MPP[30]/GE1[10] I CMOS VDD_GE_B RGMII Receive Control GE_RXCTL is presented on the rising edge of GE_RXCLK. A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK. MII/MMII Receive Data Valid GMII Receive Error MPP[31]/GE1[11] I CMOS VDD_GE_B RGMII Receive Clock The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream. MII/MMII Receive Clock Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz. Doc. No. MV-S104859-U0 Rev. E Page 30 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued) I/O P in Ty p e CMOS Power R a il VDD_GE_B D e s c r i p t io n Pin Name MPP[32]/GE1[12] I/O RGMII Transmit Clock RGMII transmit reference output clock for GE_TXD[3:0] and GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock. Not used in MII/MMII mode. MII/MMII Carrier Sense Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock. GMII Carrier Sense MPP[33]/GE1[13] t/s O CMOS VDD_GE_B RGMII Transmit Control Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge. GE_TXEN is presented on the rising edge of GE_TXCLKOUT. A logical derivative of transmit enable transmit error is presented on the falling edge of GE_TXCLKOUT. MII/MMII Transmit Error It is synchronous to transmit clock. NOTE: Multiplexed on MPP. GMII Transmit Error It Is synchronous to GE_TXCLKOUT. NOTE: Multiplexed on MPP. MPP[34]/GE1[14] O CMOS VDD_GE_B MII/MMII Transmit Enable Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock. MII/MMII Receive Error Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to GE_RXCLK input. NOTE: Multiplexed on MPP. MPP[35]/GE1[15] I CMOS VDD_GE_B Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 31 88F6281 Hardware Specifications 1.2.7 Serial Management Interface (SMI) Interface Pin Assignments Serial Management Interface (SMI) Pin Assignments I/O P in Ty p e CMOS/ Power R a il VDD_GE_A D e s c r i p t io n Table 9: Pin Name GE_MDC t/s O Management Data Clock MDC is derived from TCLK divided by 128. Provides the timing reference for the transfer of the MDIO signal. Management Data In/Out Used to transfer control and status information between PHY devices and the GbE controller. NOTE: An external pullup is required. GE_MDIO t/s I/O CMOS VDD_GE_A Doc. No. MV-S104859-U0 Rev. E Page 32 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.8 USB 2.0 Interface Pin Assignments Table 10: USB 2.0 Interface Pin Assignments Pin Name I/O Pi n Ty p e CML P ow e r R ai l USB_AVDD D e s c r ip t i o n USB_DP USB_DM I/O USB 2.0 Data Differential Pair Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 33 88F6281 Hardware Specifications 1.2.9 JTAG Interface Pin Assignment Table 11: JTAG Pin Assignment Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n JT_CLK I JTAG Clock Clock input for the JTAG controller. NOTE: This pin is internally pulled down to 0. JTAG Reset When asserted, resets the JTAG controller. NOTE: This pin is internally pulled down to 0.1 CPU JTAG Mode Select Controls CPU JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. Core JTAG Mode Select Controls the Core JTAG controller state. Sampled with the rising edge of JT_CLK. NOTE: This pin is internally pulled up to 1. JTAG Data Out Driven on the falling edge of JT_CLK. JTAG Data In JTAG serial data input. Sampled with the JT_CLK rising edge. NOTE: This pin is internally pulled up to 1. JT_RSTn I CMOS VDDO JT_TMS_CPU I CMOS VDDO JT_TMS_CORE I CMOS VDDO JT_TDO O CMOS VDDO JT_TDI I CMOS VDDO 1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles. Doc. No. MV-S104859-U0 Rev. E Page 34 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.10 Real Time Clock (RTC) Interface Pin Assignments Table 12: RTC Interface Pin Assignments Pin Name RTC_XIN RTC_XOUT I/O I O P in Ty p e Analog Analog Power R a il RTC_AVDD RTC_AVDD D e s c r i p t io n RTC Crystal Clock Input RTC Crystal Clock Feedback Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 35 88F6281 Hardware Specifications 1.2.11 NAND Flash Interface Pin Assignment Table 13: NAND Flash Interface Pin Assignment Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n NF_IO[7:0] I/O Data Input/Output Used to output command, address and data, and to input data during read operations. NOTE: All of the NF_IO pins are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51) Command Latch Enable Controls the activating path for commands sent to the command register. Address Latch Enable Controls the activating path for the address to the internal address registers. Chip Enable Controls the device selection. Read Enable Controls the serial data-in. Write Enable Controls writes to the NF_IO[7:0] ports. NF_CLE O CMOS VDDO NF_ALE O CMOS VDDO NF_CEn O CMOS VDDO NF_REn O CMOS VDDO NF_WEn O CMOS VDDO Doc. No. MV-S104859-U0 Rev. E Page 36 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.12 MPP Interface Pin Assignment Table 14: MPP Interface Pin Assignment Pin Name I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n MPP[19:0] t/s I/O t/s I/O t/s I/O Multi Purpose Pin Various functionalities Multi Purpose Pin Various functionalities Multi Purpose Pin Various functionalities MPP[35:20] CMOS VDD_GE_B MPP[49:36] CMOS VDDO The various functionalities of the MPP pins are detailed in Section 4, Pin Multiplexing, Note on page 51. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 37 88F6281 Hardware Specifications 1.2.13 Two-Wire Serial Interface (TWSI) Interface All of the TWSI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Note on page 51). Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment Pin Name TW_SDA I/O o/d I/O P in Ty p e CMOS Power R a il VDDO D e s c r i p t io n TWSI Port Serial Data Address or write data driven by the TWSI master or read response data driven by the TWSI slave. NOTE: Requires a pull-up resistor to VDDO. TWSI Port Serial Clock Serves as output when acting as an TWSI master. Serves as input when acting as an TWSI slave. NOTE: Requires a pull-up resistor to VDDO. TW_SCK o/d I/O CMOS VDDO Doc. No. MV-S104859-U0 Rev. E Page 38 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.14 UART Interface All of the UART signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Note on page 51). Table 16: UART Port 0/1 Interface Pin Assignment Pin Name UA0/1_RXD UA0/1_TXD UA0/1_CTS UA0/1_RTS I/O I O I O P in Ty p e CMOS CMOS CMOS CMOS Power R a il VDDO VDDO VDDO VDDO D e s c r i p t io n UART Port 0/1 RX Data UART Port 0/1 TX Data Clear to Send Request to Send Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 39 88F6281 Hardware Specifications 1.2.15 Audio (S/PDIF / I2S) Interface All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). If the Audio interface is not used, leave all of the signals unconnected. The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option. Note Table 17: Audio (S/PDIF / I2S) Interface Signal Assignment Pin Name AU_SPDIFI AU_SPDIFO AU_ SPDFRMCLK I/O I O O P in Ty p e CMOS CMOS CMOS Power R a il VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B D e s c r i p t io n S/PDIF In S/PDIF Out S/PDIF Recovered Master Clock (256 x Fs)1 For the frequency of this clock, see the Audio External Reference Clock section of Table 45, Reference Clock AC Timing Specifications, on page 86. I2S Bit Clock (64 x Fs) Transmitter Data Out I2S Left/Right Clock (1 x Fs) I2S Master Clock (256 x Fs) I2S Receiver Data In External Audio Clock For the frequency of this clock, see the Audio External Reference Clock section of Table 45, Reference Clock AC Timing Specifications, on page 86. AU_I2SBCLK AU_I2SDO AU_I2SLRCLK AU_I2SMCLK AU_I2SDI AU_EXTCLK O O O O I I CMOS CMOS CMOS CMOS CMOS CMOS VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B 1. Fs is the audio sample rate. Doc. No. MV-S104859-U0 Rev. E Page 40 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.16 Serial Peripheral Interface (SPI) Interface All of the SPI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Note on page 51). Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment Pin Name I/O 1 Pin Type Power Rail Description SPI_MOSI O I O O CMOS CMOS CMOS CMOS VDDO VDDO VDDO VDDO SPI Data Output Data is output from the master and input to the slave. SPI Data Input Data is input to the master and output from the slave. SPI Clock SPI Chip Select NOTE: This pin requires an external pull up. SPI_MISO2 SPI_SCK SPI_CSn 1. MOSI = Master Out Slave In. 2. MISO = Master In Slave Out. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 41 88F6281 Hardware Specifications 1.2.17 Secure Digital Input/Output (SDIO) Interface All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Note on page 51). Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment Pin Name I/O Pin Type Power Rail Description SD_CLK SD_CMD O I/O CMOS CMOS VDDO VDDO SDIO Clock SDIO Command Used to transfer a command serially from the SDIO host to the SDIO device. Used to transfer a command response serially from the SDIO device to the SDIO host. NOTE: This pin requires a pull up on board. SDIO Data Input/Output Used to transfer data from the SDIO host to the SDIO device or vice versa. NOTE: These pins require a pull up on board. SD_D[3:0] I/O CMOS VDDO Doc. No. MV-S104859-U0 Rev. E Page 42 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.18 Time Division Multiplexing (TDM) Interface All of the TDM signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option (see Section 4, Pin Multiplexing, on page 51). Note Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment Pin Name I/O Pin Type Power Rail Description TDM_CH0_TX_ QL TDM_CH2_TX_ QL TDM_CH0_RX_ QL TDM_CH2_RX_ QL TDM_CODEC_ INTn TDM_CODEC_ RSTn TDM_PCLK TDM_FS TDM_DRX TDM_DTX TDM_SPI_CS[1:0] O O O O I O I/O I/O I O O CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B VDDO/ VDD_GE_B TDM Channel0 Transmit Qualifier TDM Channel2 Transmit Qualifier TDM Channel0 Receive Qualifier TDM Channel2 Receive Qualifier Interrupt Signal FROM the SLIC/codec SLIC/codec Reset Signal PCM Audio Bit Clock TDM Frame Sync Signal PCM Audio Input Data (for recording) PCM Audio Output Data (for playback) Active low SPI chip selects driven by the host to the codec for register access. Always asserted for eight SCLK cycles at a time. Only Byte-by-Byte mode codec register read/write is supported. Serial SPI clock from the host to the codec for register access. This is an RTO (return to one) clock. It toggles for eight cycles at a time (for 1 byte transfer) during codec register access, then it returns to high. The host drives write data on TDM_SPI_MOSI on the negative edge of TDM_SPI_SCK, and captures read data from the codec on the positive edge of TDM_SPI_SCK. TDM_SPI_SCK O CMOS Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 43 88F6281 Hardware Specifications Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued) Pin Name I/O Pin Type Power Rail Description TDM_SPI_MOSI O CMOS VDDO/ VDD_GE_B Serial SPI data from the host to the codec for register access. When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. In a byte, the data can be driven MSB or LSB first. Serial SPI read data from the CODEC to the host for register access. When TDM_SPI_CS is asserted low, this data is driven from CODEC on negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. The CODEC drives data on this line only for a read operation, when it gets command and address in previous bytes from the host on TDM_SPI_MOSI In a byte, the data can be driven MSB or LSB first. TDM_SPI_MISO I CMOS VDDO/ VDD_GE_B Doc. No. MV-S104859-U0 Rev. E Page 44 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.19 Transport Stream (TS) Interface All of the TS signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51). The TS signals are powered on VDDO or on VDD_GE_B based on the pin multiplexing option (see Section 4, Pin Multiplexing ). Note Table 21: Transport Stream (TS) Interface Signal Assignment Pin Name I/O Pin Type Power Rail Description TSMP[0] I CMOS VDDO/ VDD_GE_B VDDO/ VDD_GE_B EXT_CLK External clock that can be used to drive the TS0_CLK and TS1_CLK TS0_CLK Port0 TS clock. * If TS0_VAL is used, the clock may be continuous. * If TS0_VAL is not used, the clock may toggle only when valid data is available on TS0_DATA. TS0_SYNC Port0 Sync/Frame Start Indicator or Packet Clock. The TS0_SYNC in parallel mode is a pulse that is active during the first (Sync) byte of the TS packet. In serial mode, the TS0_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low. TS0_VAL Port0 Valid Data Indicator When this signal is used and is valid, it indicates that valid data is present on TS0_DATA. TS0_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS0_VAL is programmable to be either active high or active low. TS0_ERR Port0 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and therefore should not be used. In output mode, the TS0_ERR is active during the entire TS frame. TS0_DATA[0] Port0 TS Data bit 0 in both parallel and serial modes. In Serial mode TS0_DATA[0] is used as data input or output. * * Parallel Mode: TS0_DATA[1]: Port0 TS Data bit 1 Serial Mode: TS1_CLK: Port1 TS clock. - If TS1_VAL is used, the clock may be continuous. - If TS1_VAL is not used, the clock may toggle only when valid data is available on TS1_DATA TSMP[1] I/O CMOS TSMP[2] I/O CMOS VDDO/ VDD_GE_B TSMP[3] I/O CMOS VDDO/ VDD_GE_B TSMP[4] I/O CMOS VDDO/ VDD_GE_B TSMP[5] I/O CMOS VDDO/ VDD_GE_B VDDO/ VDD_GE_B TSMP[6] I/O CMOS Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 45 88F6281 Hardware Specifications Table 21: Transport Stream (TS) Interface Signal Assignment (Continued) Pin Name I/O Pin Type Power Rail Description TSMP[7] I/O CMOS VDDO/ VDD_GE_B * * Parallel Mode: TS0_DATA[2]: Port0 TS Data bit 2 Serial Mode: TS1_SYNC: Port1 Sync/Frame Start Indicator or Packet Clock. The TS1_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low Parallel Mode: TS0_DATA[3]: Port0 TS Data bit 3 Serial Mode: TS1_VAL: Port1Valid Data Indicator When this signal is used and is valid, it indicates that valid data is present on TS1_DATA[0]. TS1_VAL is active during the TS frame packet data and inactive when there is no TS synchronization. In output mode, the polarity of TS1_VAL is programmable to be either active high or active low. Parallel Mode: TS0_DATA[4]: Port0 TS Data bit 4 Serial Mode: TS1_ERR: Port1 Uncorrectable Packet Error When this signal is used, an error indicates that the packet contains an uncorrectable error, and, therefore, should not be used. In output mode the TS1_ERR is active during the entire TS frame. Parallel Mode: TS0_DATA[5]: Port0 TS Data bit 5 Serial Mode: TS1_DATA[0]: Port1 TS Data bit 0, used as data input or output. TSMP[8] I/O CMOS VDDO/ VDD_GE_B * * TSMP[9] I/O CMOS VDDO/ VDD_GE_B * * TSMP[10] I/O CMOS VDDO/ VDD_GE_B * * TSMP[11] I/O CMOS VDDO/ VDD_GE_B VDDO/ VDD_GE_B TS0_DATA[6] Port0 TS Data bit 6 This pin is only valid in Parallel mode. TS0_DATA[7] Port0 TS Data bit 7 This pin is only valid in Parallel mode. TSMP[12] I/O CMOS Doc. No. MV-S104859-U0 Rev. E Page 46 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin and Signal Descriptions Pin Descriptions 1.2.20 Precise Timing Protocol (PTP) Interface All of the PTP signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, Note on page 51). Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment Pin Name I/O Pin Type Power Rail Description PTP_CLK PTP_EVENT_REQ PTP_TRIG_GEN I I O CMOS CMOS CMOS VDDO VDDO VDDO PTP Clock Trigger generation to the PTP core. Trigger generated by the PTP core. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 47 88F6281 Hardware Specifications 1.3 Internal Pull-up and Pull-down Pins Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins. The internal pull-up and pull-down resistor value is 50 k. An external resistor with a lower value can override this internal resistor. Table 23: Internal Pull-up and Pull-down Pins P in N a m e GE_TXD[0] GE_TXD[1] GE_TXD[2] GE_TXD[3] GE_TXCTL GE_MDC JT_TMS_CORE JT_RSTn JT_TDI JT_TMS_CPU NF_ALE NF_REn NF_CLE NF_CEn NF_WEn MRn MPP[1] MPP[2] MPP[3] MPP[4] MPP[5] MPP[7] MPP[10] MPP[11] MPP[12] MPP[14] MPP[18] MPP[19] MPP[33] P i n N um b e r H02 H01 H03 H04 J04 L03 T14 T15 R14 V15 R10 U11 R11 V11 V12 F04 V08 V07 V09 T09 T10 R06 R07 T07 U12 V13 V10 U10 N03 Pu ll up / Pu ll do w n Pull down Pull down Pull up Pull up Pull down Pull up Pull up Pull down Pull up Pull up Pull up Pull down Pull down Pull up Pull up Pull up Pull down Pull down Pull down Pull up Pull up Pull up Pull down Pull up Pull down Pull up Pull up Pull up Pull down Doc. No. MV-S104859-U0 Rev. E Page 48 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Unused Interface Strapping 2 Ethernet SMI MPP Unused Interface Strapping Table 24 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected). Table 24: Unused Interface Strapping Unused Interface Str a pp i ng Pull up GE_MDIO. Configure any unused MPP pin to GPIO output. Leave the power supply connected. * If the related power supply is VDDO, leave it connected to 3.3V. * If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V. Discard the power filter. Leave USB_AVDD connected to 3.3V. All other signals can be left unconnected. Discard the analog power filters. Leave PEX_AVDD connected to 1.8V. Pull down the PEX_CLK_N signal through a 50 k resistor to GND. Pull up the PEX_CLK_P signal through a 16 k resistor to 1.8V. All other signals can be left unconnected. Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Table 32, Reset Configuration, on page 67. Discard the analog power filters. SATA0_AVDD/SATA1_AVDD can be left unconnected. Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND. Discard the power filter. Leave SSCG_AVDD connected to 1.8V. Connect VHV to VDD USB PCI Express SATA RTC SSCG eFuse Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 49 88F6281 Hardware Specifications 3 88F6281 Pin Map and Pin List The 88F6281 pin list is provided as an Excel file attachment. To open the attached Excel pin list file, double-click the pin icons below: 88F6281 Pin Map and Pin List.xls File attachments are only supported by Adobe Reader 6.0 and above. Note To download the latest version of free Adobe Reader go to http://www.adobe.com. Doc. No. MV-S104859-U0 Rev. E Page 50 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin Multiplexing Multi-Purpose Pins Functional Summary 4 4.1 Pin Multiplexing Multi-Purpose Pins Functional Summary The 88F6281 device contains 50 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register. General Purpose pins: MPP[5:0] and MPP[49:7]: * GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and MPP[49:34] * GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], MPP[19:18], and MPP[33] SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output. SYSRST_OUTn is the default setting for MPP[6]. PEX_RST_OUTn: Optional PCI Express Endpoint card reset output. MII/MMII/GMII/RGMII interface signals SATA0/1_ACTn/SATA0/1_PRESENTn (port 0 and port 1): SATA active and SATA present indications--see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. NF_IO[7:0] (NAND Flash data [7:0]) SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn UART interface (port 0 and port 1): Transmit and receive functions: UA0_TXD, UA0_RXD, UA1_TXD, UA1_RXD, and Modem control functions: UA0_RTSn, UA0_CTSn, UA1_RTSn, UA1_CTSn SDIO interface: SD_CLK, SD_CMD, SD_D[3:0] Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK, AU_I2SBCLK, AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK TS (Transport Stream) interface signals: TSMP[12:0] TDM/SPI interface signals: TDM_CH0/2_TX_QL, TDM_CH0/2_RX_QL, TDM_SPI_CS0/1, TDM_SPI_SCK, TDM_SPI_MOSI, TDM_SPI_MISO, TDM_CODEC_INTn, TDM_CODEC_RSTn, TDM_PCLK, TDM_FS, TDM_DRX, TDM_DTX PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK TWSI signals: TW_SDA, TW_SCK Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 51 88F6281 Hardware Specifications MPP pins can be assigned to different functionalities through the MPP Control register, as shown in Table 25. Table 25: MPP Functionality MPP[19:0]: GPIO SATA LEDs NAND flash TWSI UART SPI PTP SDIO MPP[35:20]: GPIO SATA LEDs GbE Audio TDM TS PTP M P P [ 4 9 : 3 6] : GPIO Audio TDM TS Table 26 lists the functionality of the MPP pins, as determined by the MPP Multiplex register, see the Pins Multiplexing Interface Registers section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Doc. No. MV-S104859-U0 Rev. E Page 52 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin Multiplexing Multi-Purpose Pins Functional Summary Table 26: MPP Function Summary Pin name 0x0 GPIO[0] (in/out) GPO[1] (out only) GPO[2] (out only) GPO[3] (out only) GPIO[4] (in/out) GPO[5] (out only) 0x1 NF_IO[2] (in/out) NF_IO[3] (in/out) NF_IO[4] (in/out) NF_IO[5] (in/out) NF_IO[6] (in/out) NF_IO[7] (in/out) 0x2 SPI_SCn (out) SPI_MOSI (out) SPI_SCK (out) SPI_MISO (in) UA0_RXD (in) UA0_TXD (out) 0x3 0x4 0x5 0xC 0xD MPP[0] - - - - - MPP[1] - - - - - MPP[2] - - - - - MPP[3] - - SATA1_AC Tn (out) - PTP_CLK (in) - MPP[4] - - - MPP[5] - PTP_TRIG_ SATA0_AC GEN (out) Tn (out) - - MPP[6] SYSRST_O SPI_MOSI PTP_TRIG_ UTn (out) (out) GEN (out) SPI_SCn (out) UA0_RTS (out) UA0_CTS (in) SPI_SCK (out) SPI_MISO (in) PTP_TRIG_ GEN (out) UA1_RTS (out) UA1_CTS (in) UA0_TXD (out) - - MPP[7] GPO[7] (out PEX_RST_ only) OUTn (out) GPIO[8] (in/out) GPIO[9] (in/out) GPO [10] (out only) GPIO[11] (in/out) GPO[12] (out only) GPIO[13] (in/out) GPIO[14] (in/out) GPIO[15] (in/out) GPIO[16] (in/out) GPIO[17] (in/out) TW_SDA (in/out) TW_SCK (in/out) - MII0_RXER R (in) - - - - MPP[8] MPP[9] SATA1_PR PTP_CLK MII0_COL ESE NTn (in) (in) (out) SATA0_PR PTP_EVEN MII0_CRS ESE NTn T_REQ (in) (in) (out) SATA1_AC PTP_TRIG_ Tn (out) GEN (out) PTP_clk (in) - MPP[10] - MPP[11] SD_CLK (out) SD_CMD (in/out) SD_D[0] (in/out) SD_D[1] (in/out) SD_D[2] (in/out) SD_D[3] (in/out) UA0_RXD PTP_EVEN SATA0_AC PTP_TRIG_ (in) T_REQ (in) Tn (out) GEN (out) UA1_TXD (out) UA1_RXD (in) UA1_TXD (out) UA1_RXD (in) - MPP[12] MPP[13] - SATA1_PR ESE NTn (out) SATA0_AC Tn (out) SATA1_AC Tn (out) SATA0_PR ESE NTn (out) - - MII0_COL (in) MII0_CRS (in) - MPP[14] UA0_RTS (out) UA0_CTS (in) - - - MPP[15] - - MPP[16] - - MPP[17] - - Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 53 88F6281 Hardware Specifications Table 26: MPP Function Summary (Continued) Pin name MPP[18] 0x0 GPO[18] (out only) GPO[19] (out only) GPIO[20] (in/out) GPIO[21] (in/out) GPIO[22] (in/out) GPIO[23] (in/out) GPIO[24] (in/out) GPIO[25] (in/out) GPIO[26] (in/out) GPIO[27] (in/out) GPIO[28] (in/out) GPIO[29] (in/out) GPIO[30] (in/out) GPIO[31] (in/out) GPIO[32] (in/out) GPO[33] (out only) GPIO[34] (in/out) GPIO[35] (in/out) 0x1 NF_IO[0] (in/out) NF_IO[1] (in/out) TSMP[0] (in/out) TSMP[1] (in/out) TSMP[2] (in/out) TSMP[3] (in/out) TSMP[4] (in/out) TSMP[5] (in/out) TSMP[6] (in/out) TSMP[7] (in/out) TSMP[8] (in/out) TSMP[9] (in/out) 0x2 0x3 0x4 0x5 0xC 0xD - MPP[19] TDM_CH0_ TX_QL (out) TDM_CH0_ RX_QL (out) TDM_CH2_ TX_QL (out) TDM_CH2_ RX_QL (out) TDM_SPI_ CS0 (out) TDM_SPI_ SCK (out) TDM_SPI_ MISO (in) TDM_SPI_ MOSI (out) TDM_COD EC_INTn (in) TDM_COD EC_RSTn (out) - - - - - MPP[20] GE1[0] AU_SPDIFI SATA1_AC (in) Tn (out) AU_SPDIF SATA0_AC O (out) Tn (out) AU_SPDIF SATA1_PR RMCLK(out ESENTn ) (out) SATA0_PR AU_I2SBCL ESENTn K (out) (out) AU_I2SDO (out) AU_I2SLRC LK (out) AU_I2SMC LK (out) AU_I2SDI (in) AU_EXTCL K (in) - - - MPP[21] GE1[1] - - MPP[22] GE1[2] - - MPP[23] GE1[3] - - MPP[24] GE1[4] - - MPP[25] GE1[5] - - - MPP[26] GE1[6] - - - MPP[27] GE1[7] - - - MPP[28] GE1[8] - - - MPP[29] GE1[9] - - - MPP[30] TSMP[10] TDM_PCLK (in/out) (in/out) TSMP[11] (in/out) TSMP[12] (in/out) TDM_FS (in/out) TDM_DRX (in) TDM_DTX (out) TDM_SPI_ CS1 (out) TDM_CH0_ TX_QL (out) GE1[10] - - - - MPP[31] GE1[11] - - - - MPP[32] GE1[12] - - - - MPP[33] GE1[13] - SATA1_AC Tn (out) - - MPP[34] - GE1[14] - - - MPP[35] - GE1[15] - SATA0_AC MII0_RXER Tn (out) R (in) - Doc. No. MV-S104859-U0 Rev. E Page 54 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin Multiplexing Multi-Purpose Pins Functional Summary Table 26: MPP Function Summary (Continued) Pin name MPP[36] 0x0 GPIO[36] (in/out) GPIO[37] (in/out) GPIO[38] (in/out) GPIO[39] (in/out) GPIO[40] (in/out) GPIO[41] (in/out) GPIO[42] (in/out) GPIO[43] (in/out) GPIO[44] (in/out) GPIO[45] (in/out) GPIO[46] (in/out) GPIO[47] (in/out) GPIO[48] (in/out) GPIO[49] (in/out) 0x1 TSMP[0] (in/out) TSMP[1] (in/out) TSMP[2] (in/out) TSMP[3] (in/out) TSMP[4] (in/out) TSMP[5] (in/out) TSMP[6] (in/out) TSMP[7] (in/out) TSMP[8] (in/out) TSMP[9] (in/out) TSMP[10] (in/out) TSMP[11] (in/out) TSMP[12] (in/out) 0x2 TDM_SPI_ CS1 (out) TDM_CH2_ TX_QL (out) TDM_CH2_ RX_QL (out) TDM_SPI_ CS0 (out) TDM_SPI_ SCK (out) TDM_SPI_ MISO (in) TDM_SPI_ MOSI (out) TDM_COD EC_INTn (in) TDM_COD EC_RSTn (out) TDM_PCLK (in/out) TDM_FS (in/out) TDM_DRX (in) TDM_DTX (out) TDM_CH0_ RX_QL (out) 0x3 0x4 AU_SPDIFI (in) AU_SPDIF O (out) AU_SPDIF RMCLK (out) AU_I2SBCL K (out) AU_I2SDO (out) AU_I2SLRC LK (out) AU_I2SMC LK (out) AU_I2SDI (in) AU_EXTCL K (in) 0x5 0xC 0xD - MPP[37] - - - - MPP[38] - - - - MPP[39] - - - - MPP[40] - - - - MPP[41] - - - - MPP[42] - - - - MPP[43] - - - - MPP[44] - - - - MPP[45] - - - - MPP[46] - - - - - MPP[47] - - - - - MPP[48] - - PTP_CLK (in) - - MPP[49] - - - - Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 55 88F6281 Hardware Specifications For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset depends on Boot mode (see the Boot Device field in Table 32, Reset Configuration, on page 67): Note * When Boot mode is NAND Flash, MPP[5:0] and MPP[19:18] wake up after reset in NAND Flash mode. * When Boot mode is SPI Flash, either MPP[3:0] or {MPP[3:1] and MPP[7]} wake up after reset in SPI mode, (according to boot mode configured by reset strap pins). Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn) Pin MPP[7] wakes up after reset: * As SPI_CSn, if the boot device--selected according to boot device reset strapping--is 0x2 (boot from SPI flash, SPI_CSn on MPP[7]). * As PEX_RST_OUTn, if the boot device--selected according to boot device reset strapping--is any option other than 0x2. When TWSI serial ROM initialization is enabled (see TWSI Serial ROM Initialization in Table 32, Reset Configuration, on page 67), MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively. All other MPP interface pins wake up after reset in 0x0 mode (GPIO/GPO) and are default set to Data Output disabled (Tri-State). Therefore, those MPPs that are GPIO are in fact inputs, and those that are GPO are Tri-State. The SPI interface can be configured using one of the following sets of MPP pins: * MPP[3:0] * MPP[11], MPP[10], MPP[7], and MPP[6] * MPP[3:1] and MPP[7] Do not configure both MPP[3] and MPP[11] as SPI_MISO. UART0 and UART1 signals are duplicated on a few MPPs. The UART0 or UART1 signals must not be configured to more than one MPP. When selecting the MII/MMII interface (MPP[35:20]) and the TDM interface (MPP[49:35]), the TDM signal TDM_CH0_TX_QL and the MII/MMII signal MII1_RXERR are both multiplexed on MPP[35]. However, MPP[35] can only be configured to one of these functions at a time. Some of the MPP pins are sampled during SYSRSTn de-assertion to set the device configuration. These pins must be set to the correct value during reset (see Section 6.5, Pins Sample Configuration, on page 66). Pins that are left as GPIO and are not connected should be set to output after SYSRSTn de-assertion. Doc. No. MV-S104859-U0 Rev. E Page 56 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin Multiplexing Gigabit Ethernet (GbE) Pins Multiplexing on MPP 4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and an MDIO pin). For the 88F6281, additional GbE interface pins are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch. Two RGMII ports One RGMII port and one MMII/MII port (either port 0 as RGMII and port 1 as MMII/MII or port 0 as MMII/MII and port 1 as RGMII) One GMII port (port 0) Table 27 summarizes the GbE port pins multiplexing. Table 27: Ethernet Ports Pins Multiplexing Pin Name GE_TXCLKOUT GE_TXD[3:0] GE_TXCTL GE_RXD[3:0] GE_RXCTL GE_RXCLK MPP[8] or MPP[35] MPP[8] or MPP[14] MPP[9] or MPP[16] MPP [23:20] / GE1[3:0] MPP_[27:24] / GE1[7:4] MPP_28 / GE1[8] MPP_29 / GE1[9] MPP_30 / GE1[10] MPP_31 / GE1[11] MPP_32 / GE1[12] MPP_33 / GE1[13] 1x GMII GMII0_TXCLKOUT (out) GMII0_TXD[3:0] (out) GMII0_TXEN (out) GMII0_RXD[3:0] (in) GMII0_RXDV (in) GMII0_RXCLK (in) NA NA NA GMII0_TXD[7:4] (out) GMII0_RXD[7:4] (in) GMII0_COL (in) GMII0_TXCLK (in) GMII0_RXERR (in) NA GMII0_CRS (in) GMII0_TXERR (out) RGMII0 +MII1/ MM I I1 RGMII0_TXCLKOUT (out) RGMII0_TXD[3:0] (out) RGMII0_TXCTL (out) RGMII0_RXD[3:0] (in) RGMII0_RXCTL (in) RGMII0_RXCLK (in) NA NA NA MII1_TXD[3:0] (out) MII1_RXD[3:0] (in) MII1_COL (in) MII1_TXCLK (in) MII1_RXDV (in) MII1_RXCLK (in) MII1_CRS (in) MII1_TXERR (out) 2x RGMII RGMII0_TXCLKOUT (out) RGMII0_TXD[3:0] (out) RGMII0_TXCTL (out) RGMII0_RXD[3:0] (in) RGMII0_RXCTL (in) RGMII0_RXCLK (in) NA NA NA RGMII1_TXD[3:0] (out) RGMII1_RXD[3:0] (in) NA NA RGMII1_RXCTL (in) RGMII1_RXCLK (in) RGMII1_TXCLKOUT (out) RGMII1_TXCTL (out) MII0/MMII0+ R GM I I1 MII0_TXCLK (in) MII0_TXD[3:0] (out) MII0_TXEN (out) MII0_RXD[3:0] (in) MII0_RXDV (in) MII0_RXCLK (in) MII0_RXERR (in) MII0_COL (in) MII0_CRS (in) RGMII1_TXD[3:0] (out) RGMII1_RXD[3:0] (in) NA NA RGMII1_RXCTL (in) RGMII1_RXCLK (in) RGMII1_TXCLKOUT (out) RGMII1_TXCTL (out) Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 57 88F6281 Hardware Specifications Table 27: Ethernet Ports Pins Multiplexing (Continued) Pin Name MPP_34 / GE1[14] MPP_35 / GE1[15] 1x GMII NA NA RGMII0 +MII1/ MM I I1 MII1_TXEN (out) MII1_RXERR (in) 2x RGMII NA NA MII0/MMII0+ R GM I I1 NA NA Note When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals (except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) must still be configured accordingly and must have a pull-down resistor. Doc. No. MV-S104859-U0 Rev. E Page 58 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Pin Multiplexing TSMP (TS Multiplexing Pins) on MPP 4.3 TSMP (TS Multiplexing Pins) on MPP The TS interface can be configured to one of five modes: One or two serial in interfaces One or two serial out interfaces Serial in and serial out interface Parallel in interface Parallel out interface In parallel in or serial in mode, all TS signals are inputs. In parallel out or serial out mode, all TS signals are outputs. Table 28 summarizes the TS port pins multiplexing. Table 28: TS Port Pin Multiplexing Pin Name TSMP[0] TSMP[1] TSMP[2] TSMP[3] TSMP[4] TSMP[5] TSMP[6] TSMP[7] TSMP[8] TSMP[9] TSMP[10] TSMP[11] TSMP[12] Fu nc t io na li t y in TS s e r i a l m od e s 2x in/2x o ut/in +o ut EXT_CLK (in) TS0_CLK (in/out)) TS0_SYNC(in/out)) TS0_VAL (in/out)) TS0_ERR (in/out)) TS0_DATA[0] (in/out) TS1_CLK (in/out)) TS1_SYNC(in/out)) TS1_VAL (in/out)) TS1_ERR (in/out)) TS1_DATA[0] (in/out) NA NA F un c t i on a l ity i n TS pa r a l le l i n/ o ut m od e EXT_CLK (in) TS0_CLK (in/out)) TS0_SYNC(in/out)) TS0_VAL (in/out)) TS0_ERR (in/out)) TS0_DATA[0] (in/out) TS0_DATA[1] (in/out)) TS0_DATA[2] (in/out)) TS0_DATA[3] (in/out)) TS0_DATA[4] (in/out)) TS0_DATA[5] (in/out)) TS0_DATA[6] (in/out)) TS0_DATA[7] (in/out)) Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 59 88F6281 Hardware Specifications 5 Clocking Table 29 lists the clocks in the 88F6281. Table 29: 88F6281Clocks C l o ck Ty p e CPU PLL Description Reference clock: REF_CLK_XIN (25 MHz) * Derivative clocks: - CPU clock - L2 cache clock - DDR Clock (the Mbus-L uses the DDR clock.) NOTE: See Table 32, Reset Configuration, on page 67 for CPU, L2 cache and DDR frequency configuration. L2 cache clock frequency must be equal or higher then DDR clock frequency. If the SSCG enable bit in the Sampled at Reset register is set, then the SSCG circuit is applied for the CPU PLL reference clock (refer to the Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). Core PLL Reference clock: REF_CLK_XIN (25 MHz) * Derivative clocks: - TCLK (core clock, 200 MHz) - SDIO Clock (100 MHz) - Gigabit Ethernet Clock (125 MHz) - TS unit Clock(100/91/83/77MHz) - SPI clock (TCLK/30-TCLK/4 MHz) - SMI clock (TCLK/128 MHz) - TWSI clock (up to TCLK/1600) NOTE: See Table 32, Reset Configuration, on page 67 for TCLK frequency configuration. NOTE: See the TS Interface Configuration register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications for TS clock frequency configuration. There are two options for the reference clock configuration, depending on the PCI Express clock 100 MHz differential clock: * The device uses an external source for PCI Express clock. The PEX_CLK_P pin is an input. * The device uses an internal generated clock for PCI Express clock. The PEX_CLK_P pin is an output, driving out the PCI Express differential clock. * Reference clock: REF_CLK_XIN (25 MHz) * * PEX PHY USB PHY PLL Doc. No. MV-S104859-U0 Rev. E Page 60 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Clocking Table 29: 88F6281Clocks (Continued) C l o ck Ty p e SATA PHY PLL Description * * Reference clock: REF_CLK_XIN (25 MHz) Derivative clock: SATA Clock (150 MHz) RTC Reference clock: RTC_XIN (32.768 kHz) Used for real time clock functionality, see the Real Time Clock section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Reference clock: PTP_CLK (125 MHz) The PTP_CLK can be used for the following functions: * PTP time stamp clock Two options for reference clock: - PTP_CLK - Gigabit Ethernet Clock (125 MHz) * TS unit clock Two options for reference clock: - PTP_CLK/2 - Core PLL * Audio unit clock Two options for reference clock: - PTP_CLK - REF_CLK_XIN (25 MHz) For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. * * PTP The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 6.5, Pins Sample Configuration, on page 66). Table 30: Supported Clock Combinations DDR Clock (MHz) 333 250 200 400 300 267 200 375 CPU to DDR C lo c k R a t i o 3:1 4:1 5:1 3:1 4:1 4.5:1 6:1 4:1 C P U C lo c k (MHz) CPU to L2 Clock Ratio L 2 C lo c k (MHz) 1000 3:1 333 1200 3:1 400 1500 3:1 500 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 61 88F6281 Hardware Specifications 5.1 Spread Spectrum Clock Generator (SSCG) The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See SSCG Disable in Table 32, Reset Configuration, on page 67, for SSCG enable/bypass configuration settings. The SSCG block can be configured to perform up spread, down spread and center spread. The modulation frequency is configurable. Typical frequency is 30 kHz. The spread percentage can also be configured up to 1%. For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Doc. No. MV-S104859-U0 Rev. E Page 62 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary System Power Up/Down and Reset Settings Power-Up/Down Sequence Requirements 6 6.1 6.1.1 System Power Up/Down and Reset Settings This section provides information about the device power-up/down sequence and configuration at reset. Power-Up/Down Sequence Requirements Power-Up Sequence Requirements These guidelines must be applied to meet the 88F6281 device power-up requirements: The non-core voltages (I/O and Analog) as listed in Table 31 must reach 70% of their voltage level before the core voltages reach 70% of their voltage level. The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level (shown in Figure 2). The order of the power-up sequence between the core voltages (VDD and VDD_CPU) is unimportant. The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level (shown in Figure 2). The reference clock(s) inputs must toggle with their respective voltage levels before the core voltages reach 70% of their voltage level (shown in Figure 2). If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must be powered before VHV, to prevent the fuse from being accidentally burned. Table 31: I/O and Core Voltages N o n - C o r e Vo lta g e s I/ O Vo lta ge s VDD_GE_A VDD_GE_B VDD_M VDDO A n a lo g P o w e r Su p pl i es CPU_PLL_AVDD CORE_PLL_AVDD PEX_AVDD RTC_AVDD SATA0_AVDD SATA1_AVDD SSCG_AVDD XTAL_AVDD USB_AVDD VDD VDD_CPU C or e Vo l ta g es Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 63 88F6281 Hardware Specifications Figure 2: Power-Up Sequence Example Voltage Non-Core Voltage 70% of Non-Core Voltage Core Voltage 70% of Core Voltage Reset(s) Clock(s) Note It is the designer's responsibility to verify that the power sequencing requirements of other components are also met. Although the non-core voltages can be powered up any time before the core voltages, allow a reasonable time limitation (for example, 100 ms) between the first non-core voltage power-up and the last core voltage power-up. 6.1.2 Power-Down Sequence Requirements There are no special requirements for the core supply to go down before non-core power, or for reset assertion when powering down (except for VHV, as described below). However, allow a reasonable time limitation (no more than 100 ms) between the first and last voltage power-down. When using the eFuse in Burning mode, VHV must be powered down before VDD. 6.2 Hardware Reset The device has one reset input pin--SYSRSTn. When asserted, the entire chip is placed in its initial state. Most outputs are placed in high-z, except for the following output pins, that are still active during SYSRSTn assertion: M_CLKOUT, M_CLKOUTn M_CKE M_ODT[1:0] M_STARTBURST SYSRST_OUTn Doc. No. MV-S104859-U0 Rev. E Page 64 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary System Power Up/Down and Reset Settings Hardware Reset Note Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward. 6.2.1 Reset Out Signal The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic. SYSRST_OUTn is the default option for that MPP pin. This signal is asserted low for 20 ms, when one of the following maskable events occurs: Received hot reset indication from the PCI Express link (only relevant when used as a PCI Express endpoint), and bit 6.2.2 Power On Reset (POR) The SYSRST_OUTn output signal is asserted low for 20 ms, when the power-on-reset (POR) circuit is triggered. POR is triggered when VDD power up (digital core voltage) reaches a VDD threshold (threshold maximum value 0.8V). Hysteresis: Another trigger will only occur after the power first drops to 50 mV, and then a power up occurs. 6.2.3 SYSRSTn Duration Counter When SYSRSTn is asserted low, a SYSRSTn duration counter is running. The counter clock is the 25 MHz reference clock. It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds). The host software can read the counter value and reset the counter. When the counter reach its maximum value, it remains at this value until counter reset is triggered by software. Note The SYSRSTn duration counter is useful for implementing manufacturer/factory reset. Upon a long reset assertion, greater than a pre-configured threshold, the host software may reset all settings to the factory default values. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 65 88F6281 Hardware Specifications 6.3 6.3.1 PCI Express Reset PCI Express Root Complex Reset As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register's 6.3.2 PCI Express Endpoint Reset When a Hot Reset packet is received: A maskable interrupt is asserted. If the 6.4 6.5 SheevaTM CPU TAP Controller Reset The SheevaTM CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and JT_TMS_CPU is active. Pins Sample Configuration The following pins are sampled during SYSRSTn de-assertion: Internal pull up/down resistors set the default mode (see Section 1.3, Internal Pull-up and Pull-down Pins, on page 48). Higher value, external pull up/down resistors are required to change the default mode of operation. These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion). Doc. No. MV-S104859-U0 Rev. E Page 66 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary System Power Up/Down and Reset Settings Pins Sample Configuration Note If external logic is used instead of pull-up and pull-down resistors, the logic must drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion. All reset sampled values are registered in the Sample at Reset register (see the MPP Registers in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). This is useful for board debug purposes and identification of board and system settings for the host software. If a signal is pulled up on the board, it must be pulled to the proper voltage level. Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see Table 36, Recommended Operating Conditions, on page 77). In each row of Table 32, the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK Frequency Select, MPP[2] is the MSB and MPP[10] is the LSB). Table 32: Reset Configuration P in MPP[1] C on fi g ur a tio n F u n ct io n TWSI Serial ROM Initialization 0 = Disabled 1 = Enabled NOTE: Internally pulled down to 0x0. When this pin is set to 0x1, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively (see Section 4.1, Multi-Purpose Pins Functional Summary, on page 51). MPP[2],MPP[5], MPP[19], MPP[10] CPU_CLK Frequency Select 0x0-0x6 = Reserved 0x7 = 1000 MHz 0x8 = Reserved 0x9 = 1200 MHz 0xA-0xB = Reserved 0xC = 1500 MHz 0xD-0xF = Reserved NOTE: Internally pulled to 0x6. The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 67 88F6281 Hardware Specifications Table 32: Reset Configuration (Continued) P in MPP[33], NF_ALE, NF_REn, NF_CLE C on fi g ur a tio n F u n ct io n CPU_CLK to DDR CLK Ratio 0x0-0x3 = Reserved 0x4 = 3:1 0x5 = Reserved 0x6 = 4:1 0x7 = 4.5:1 0x8 = 5:1 0x9 = 6:1 0xA-0xF = Reserved NOTE: Internally pulled to 0x4. The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61. MPP[3], MPP[12], NF_WEn CPU_CLK to CPU L2 Clock Ratio 0x0 = Reserved 0x1 = 2:1 0x2 = Reserved 0x3 = 3:1 0x4-0x7 = Reserved NOTE: Internally pulled to 0x1. The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61. Doc. No. MV-S104859-U0 Rev. E Page 68 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary System Power Up/Down and Reset Settings Pins Sample Configuration Table 32: Reset Configuration (Continued) P in GE_TXD[2:0] C on fi g ur a tio n F u n ct io n Boot Device 0x0 = Reserved 0x1 = Reserved 0x2 = Boot from SPI flash (SPI_CSn on MPP[7]) 0x3 = Reserved 0x4 = Boot from SPI flash (SPI_CSn on MPP[0]) 0x5 = Boot from NAND flash 0x6 = Boot from SATA 0x7 = Boot from the PCI Express port NOTE: * Internally pulled to 0x4. * Only SPI signals configured on pins MPP[3:0] or on pins MPP[7] and MPP[3:1] can be used for booting from SPI. SPI signals that are multiplexed on other MPPs can only be used after booting (see Section 4.1, Multi-Purpose Pins Functional Summary, on page 51). * When GE_TXD[2:0] is set to 0x4, MPP[3:0] wake up as SPI signals. * When GE_TXD[2:0] is set to 0x2, MPP[7] and MPP[3:1] wake up as SPI signals. * When GE_TXD[2:0] is set to 0x5, MPP[5:0] and MPP[19:18] wake up as NAND Flash signals. * For a more detailed description of the bootROM, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. * For a more detailed description of the boot from SPI flash or NAND flash, see the SPI Interface and NAND Flash Interface sections in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. * There is an option to boot from UART when GE_TXD[2:0] = 0x2-0x7. For a more detailed description of the boot from UART, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. GE_TXD[3] SSCG Disable 0 = Enable 1 = Disable NOTE: Internally pulled to 0x1. GE_MDC PCI Express Clock (100 MHz Differential Clock) Configuration 0x0 = The device use external source for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N are inputs. 0x1 = The device uses internal generated clock for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N pins are outputs, driving out the PCI Express differential clock. NOTE: Internally pulled to 0x1. GE_TXCTL Used for internal testing Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset. MPP[7] Reserved Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 69 88F6281 Hardware Specifications Table 32: Reset Configuration (Continued) P in MPP[18] C on fi g ur a tio n F u n ct io n Reserved NOTE: MUST be externally pulled down to 0x0 during reset. 6.6 Serial ROM Initialization The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface. If serial ROM initialization is enabled, the device TWSI master starts reading initialization data from serial ROM and writes it to the appropriate registers, upon de-assertion of SYSRSTn. When using Serial ROM Initialization, the MPP[9:8] pins must be configured to as TW_SCK (MPP[9]) and TW_SDA (MPP[8]). 6.6.1 Serial ROM Data Structure Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown in Figure 3. Figure 3: Serial ROM Data Structure MSB LSB address0[31:24] address0[23:16] address0[15:8] address0[7:0] data0[31:24] data0[23:16] data0[15:8] data0[7:0] address1[31:24] address1[23:16] address1[15:8] address1[7:0] data1[31:24] data1[23:16] data1[15:8] data1[7:0] Start Doc. No. MV-S104859-U0 Rev. E Page 70 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary System Power Up/Down and Reset Settings Boot Sequence The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the 32-bit address being read, and based on address decoding result, writes the next four bytes to the required target. The Serial Initialization Last Data Register contains the expected value of last serial data item (default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence. 6.6.2 Serial ROM Initialization Operation On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 4. Figure 4: Serial ROM Read Example s t a r t w r i t e s t a r t r e a d Data from ROM Upper Byte Offset Lower Byte Offset s10100000 a c k ROM Address 00000000 a c k 00000000 a c k s10100001 a c k ROM Address Last Data from ROM AAAAAAAA a c k AAAA s t o p xxxxxxxx a c k n a c k p 11111111 a c k 11111111 a c k 11111111 a c k 11111111 For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. Initialization data must be programmed in the serial ROM starting at offset 0x0. The device assumes 7-bit serial ROM address of `b1010000. After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an additional byte of dummy data. It responds with no-ack and then asserts the stop bit. The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte ROM.). 6.7 Boot Sequence The device requires that SYSRSTn stay asserted for at least 300 s after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion: 1. While SYSRSTn is asserted, the CPU PLL and the core PLL are locked. 2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles. 3. If Serial ROM initialization is enabled, an initialization sequence is started. 4. If configured to boot from NAND flash (and BootROM is disabled), the device also performs a NAND Flash boot sequence to prepare page 0 in the NAND flash device for read. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 71 88F6281 Hardware Specifications Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see Table 32, Reset Configuration, on page 67. For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. As part of the CPU boot code, the CPU typically performs the following: Configures the PCI Express address map. Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization (sets Doc. No. MV-S104859-U0 Rev. E Page 72 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary JTAG Interface TAP Controller 7 7.1 JTAG Interface To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface. The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions. TAP Controller The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine (FSM), as defined by IEEE JTAG standard 1149.1. To place the device in a functional mode, reset the JTAG state machine to disable the JTAG interface. According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the 88F6281 SYSRSTn is asserted. The JTAG state machine can only be reset by one of the following methods: Asserting JT_RSTn. Setting JT_TMS_CORE for at least five JT_CLK cycles. To place the device in one of the boundary scan test mode, the JTAG state machine must be moved to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift instructions into the Instruction register while in SHIFT-IR state and shift data into and from the various data registers when in SHIFT-DR state. 7.2 Instruction Register The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel. Table 33 lists the instructions supported by the device. Table 33: Supported JTAG Instructions In s t r u c t io n HIGHZ IDCODE EXTEST C o de 0011 0010 0000 D es c r ip t i o n Select the single bit Bypass register between TDI and TDO. Sets the device output pins to high-impedance state. Selects the Identification register between TDI and TDO. This 32-bit register is used to identify the device. Selects the Boundary Scan register between TDI and TDO. Outputs the boundary scan register cells to drive the output pins of the device. Inputs the boundary scan register cell to sample the input pin of the device. Selects the Boundary Scan register between TDI and TDO. Samples input pins of the device to input boundary scan register cells. Preloads the output boundary scan register cells with the Boundary Scan register value. Selects the single bit Bypass register between TDI and TDO. This allows for rapid data movement through an untested device. SAMPLE/PRE LOAD 0001 BYPASS 1111 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 73 88F6281 Hardware Specifications 7.3 Bypass Register The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0 when the TAP FSM is in the Capture-DR state. 7.4 JTAG Scan Chain The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to sequentially access all of the data pins both for driving and strobing data. For further details, refer to the BSDL Description file for the device. 7.5 ID Register The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID register is shown in Table 34, which describes the various ID Code fields. Table 34: IDCODE Register Map B i ts 31:28 27:12 11:1 0 Va l u e 0x0 0x6281 0x1AB 1 Description Version (4'b0010 for version A0, 4'b0011 for A1, etc.) Part number Manufacturer ID Mandatory Doc. No. MV-S104859-U0 Rev. E Page 74 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications (Preliminary) Absolute Maximum Ratings 8 8.1 Electrical Specifications (Preliminary) The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE. Note Absolute Maximum Ratings Table 35: Absolute Maximum Ratings Parameter VDD VDD_CPU CPU_PLL_AVDD CORE_PLL_AVDD SSCG_AVDD Min -0.5 -0.5 -0.5 Max 1.2 1.32 2.2 U n its V V V C om m e n ts Core voltage CPU interface Analog supply for the internal PLL -0.5 2.2 V Analog supply for: Internal Spread Spectrum Clock Generator I/O voltage for: RGMII/GMII/MII/MMII/SMI interface I/O voltage for: SDRAM interface I/O voltage for: MPP, TWSI, JTAG, SDIO, I2S, SPI, TS, and TDM interfaces I/O voltage for eFuse burning Analog supply for: PCI Express interface Analog supply for: USB interface Analog supply for: SATA interface Analog supply for internal clock inverter for crystal support and current source for SATA and USB PHYs VDD_GE_A VDD_GE_B VDD_M -0.5 4.0 V -0.5 2.2 V VDDO -0.5 4.0 V VHV PEX_AVDD -0.5 -0.5 3.0 2.2 V V USB_AVDD -0.5 4.0 V SATA0_AVDD SATA1_AVDD XTAL_AVDD -0.5 4.0 V -0.5 2.2 V Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 75 88F6281 Hardware Specifications Table 35: Absolute Maximum Ratings (Continued) Parameter RTC_AVDD Min -0.5 Max 2.2 U n its V C om m e n ts Analog supply for: RTC interface Case temperature Storage temperature TC TSTG -40 -40 125 125 C C Caution Exposure to conditions at or beyond the maximum rating may damage the device. Operation beyond the recommended operating conditions (Table 36) is neither recommended nor guaranteed. Doc. No. MV-S104859-U0 Rev. E Page 76 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications (Preliminary) Recommended Operating Conditions 8.2 Recommended Operating Conditions Table 36: Recommended Operating Conditions Parameter VDD VDD_CPU CPU_PLL_AVDD CORE_PLL_AVDD SSCG_AVDD M in 0.95 1.05 1.7 Ty p 1.0 1.1 1.8 Max 1.05 1.15 1.9 Units V V V C om m e n ts Core voltage CPU interface Analog supply for the internal PLL 1.7 1.8 1.9 V Analog supply for: Internal Spread Spectrum Clock Generator I/O voltage for: RGMII(10/100 RGMII only)/ GMII/MII/MMII/SMI interfaces I/O voltage for: RGMII/SMI interfaces I/O voltage for: SDRAM interface I/O voltage for: MPP, TWSI, JTAG, SDIO, I2S, SPI, TS, and TDM interfaces VDD_GE_A VDD_GE_B 3.15 3.3 3.45 V 1.7 1.8 1.9 V VDD_M 1.7 1.8 1.9 V VDDO 3.15 3.3 3.45 V VHV (during eFuse Burning mode) 2.375 2.5 2.625 V I/O voltage for eFuse burning NOTE: If the VHV voltage is higher than VDD voltage (burning mode), VDD must be powered before VHV, to prevent the fuse from being accidentally burned. I/O voltage for eFuse reading NOTE: It is recommended that if only a read operation is required, VHV would be connected to the device VDD power. Analog supply for: PCI Express interface Analog supply for: USB interface Analog supply for: SATA interface VHV (during eFuse Reading mode) 0.95 1.0 1.05 V PEX_AVDD 1.7 1.8 1.9 V USB_AVDD 3.15 3.3 3.45 V SATA0_AVDD SATA1_AVDD 3.15 3.3 3.45 V Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 77 88F6281 Hardware Specifications Table 36: Recommended Operating Conditions (Continued) Parameter XTAL_AVDD M in 1.7 Ty p 1.8 Max 1.9 Units V C om m e n ts Analog supply for: Internal clock inverter for crystal support and current source for SATA and USB PHYs Analog supply for RTC in Regular mode Analog supply for RTC in Battery Back-up mode Junction Temperature RTC_AVDD 1.7 1.8 1.9 V 1.3 1.5 1.7 V TJ 0 105 C Caution Operation beyond the recommended operating conditions is neither recommended nor guaranteed. Doc. No. MV-S104859-U0 Rev. E Page 78 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications (Preliminary) Thermal Power Dissipation 8.3 Thermal Power Dissipation Before designing a system, Marvell recommends reading application note AN-63: Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products. Note The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design. . Table 37: Thermal Power Dissipation In t e r f a c e Core (VDD 1.0V) Embedded CPU (VDD_CPU 1.1V) S y m bo l PVDD PVDD_CPU Te s t C on d it io n s TCLK @ 200 MHz Ty p 280 790 Units mW mW CPU @ 1000 MHz, L2 @ 333 MHz CPU @ 1200 MHz, L2 @ 400 MHz CPU @ 1500 MHz, L2 @ 500 MHz 870 mW 1050 mW RGMII 1.8V interface RGMII (10/100 RGMII only) 3.3V interface GMII 3.3V interface MII/MMII 3.3V interface Miscellaneous interfaces (JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI) DDR2 SDRAM interface (On-board, 16-bit, 400 MHz) eFuse during Burning mode NOTE: Since the eFuse burn is performed only once, there is no thermal effect after the burn has finished. eFuse during Reading mode PCI Express interface USB interface SATA interface PRGMII PRGMII PGMII PMII PMISC 30 50 50 10 50 mW mW mW mW mW PDDR2 PFUSE Four on board devices, 75 ohm ODT termination 250 mW 50 mW PFUSE PPEX PUSB PSATA Both SATA ports 25 100 120 410 mW mW mW mW Notes: 1. The values are for nominal voltage. 2. Power in mW is calculated using the typical recommended VDDIO specification for each power rail. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 79 88F6281 Hardware Specifications 8.4 Current Consumption The purpose of the Current Consumption table is to support board power design and power module selection. . Table 38: Current Consumption In t e r f a c e Core (VDD 1.0V) Embedded CPU (VDD_CPU 1.1V) S y m bo l IVDD IVDD_CPU Te s t C on d it io n s TCLK @ 200 MHz Max 600 1920 Units mA mA CPU @ 1000 MHz, L2 @ 333 MHz CPU @ 1200 MHz, L2 @ 400 MHz CPU @ 1500 MHz, L2 @ 500 MHz 2010 mA 2100 mA RGMII 1.8V or 3.3V interface GMII 3.3V interface MII/MMII 3.3V interface Miscellaneous interfaces (JTAG, TWSI, UART, NAND flash, Audio, SDIO, TDM, TS, and SPI) DDR2 SDRAM interface (16-bit 400 MHz) IRGMII IGMII IMII_MMII IMISC 25 25 25 25 mA mA mA mA IDDR2 IFUSE IFUSE IPEX IUSB ISATA Four on board devices, 75 ohm ODT termination 550 mA eFuse during Burning mode eFuse during Reading mode PCI Express interface USB interface SATA interface 20 25 50 40 Both SATA ports 130 mA mA mA mA mA Notes: 1. Current in mA is calculated using maximum recommended VDDIO specification for each power rail. 2. All output clocks toggling at their specified rate. 3. Maximum drawn current from the power supply. Doc. No. MV-S104859-U0 Rev. E Page 80 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications DC Electrical Specifications 8.5 DC Electrical Specifications See Section 1.3, Internal Pull-up and Pull-down Pins, on page 48 for internal pullup/pulldown information. Note 8.5.1 General 3.3V (CMOS) DC Electrical Specifications The DC electrical specifications in Table 39 are applicable for the following interfaces and signals: JTAG RGMII (10/100 Mbps)/GMII/MII/MMII Secure Digital Input/Output (SDIO) S/PDIF / I2S (Audio) Transport Stream (TS) NAND flash UART MPP PTP SYSRSTn In the following table, for the JTAG, SDIO, S/PDIF / I2S, TS, NAND flash, UART, PTP, and MPP interfaces, VDDIO means the VDDO power rail. For the RGMII/GMII/MII/MMII interface, VDDIO means the VDD_GE_A and VDD_GE_B power rails. Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 2.0 2.4 -10 5 Typ Max 0.8 VDDIO+0.3 0.4 10 Units Notes V V V V uA pF 1, 2 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 81 88F6281 Hardware Specifications 8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail. In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail. Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 2 mA IOH = -2 mA 0 < VIN < VDDIO Test Condition Min -0.3 0.65*VDDIO VDDIO-0.45 -10 5 Typ Max 0.35*VDDIO VDDIO+0.3 0.45 10 Units Notes V V V V uA pF 1, 2 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor. Doc. No. MV-S104859-U0 Rev. E Page 82 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications DC Electrical Specifications 8.5.3 SDRAM DDR2 Interface DC Electrical Specifications In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail. Table 41: SDRAM DDR2 Interface DC Electrical Specifications Parameter Input low level Input high level Output low level Output high level Rtt effective impedance value Symbol VIL VIH VOL VOH RTT IOL = 13.4 mA IOH = -13.4 mA See note 2 1.42 120 60 40 Deviation of VM w ith respect to VDDQ/2 Input leakage current Pin capacitance dVm IIL Cpin See note 3 0 < VIN < VDDIO -6 -10 5 150 75 50 180 90 60 6 10 Test Condition Min -0.3 VREF + 0.125 Typ Max VREF - 0.125 VDDIO + 0.3 0.28 Units Notes V V V V ohm ohm ohm % uA pF 1,2 1,2 1,2 3 4, 5 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. See SDRAM functional description section for ODT configuration. 2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately, then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively. RTT = 0 .5 I (VREF + 0.25 ) - I (VREF - 0.25 ) 3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load. 2 x Vm dVM = - 1 x 100 % VDDIO 4. While I/O is in High-Z. 5. This current does not include the current flow ing through the pullup/pulldow n resistor. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 83 88F6281 Hardware Specifications 8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical Specifications In the following table, VDDIO means the VDDO power rail. Table 42: TWSI Interface 3.3V DC Electrical Specifications Param eter Input low level Input high level Output low level Input leakage current Pin capacitance Sym bol VIL VIH VOL IIL Cpin IOL = 3 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V uA pF 1, 2 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor. 8.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical Specifications In the following table VDDIO means the VDDO power rail. Table 43: SPI Interface 3.3V DC Electrical Specifications Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 4 mA IOH = -4 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO VDDIO-0.6 -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V V uA pF 1, 2 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor. Doc. No. MV-S104859-U0 Rev. E Page 84 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications DC Electrical Specifications 8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical Specifications In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface. Table 44: TDM Interface 3.3V DC Electrical Specifications Param eter Input low level Input high level Output low level Output high level Input leakage current Pin capacitance Sym bol VIL VIH VOL VOH IIL Cpin IOL = 4 mA IOH = -4 mA 0 < VIN < VDDIO Test Condition Min -0.5 0.7*VDDIO VDDIO-0.6 -10 5 Typ Max 0.3*VDDIO VDDIO+0.5 0.4 10 Units Notes V V V V uA pF 1, 2 - Notes: General comment: See the Pin Description section for internal pullup/pulldow n. 1. While I/O is in High-Z. 2. This current does not include the current flow ing through the pullup/pulldow n resistor. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 85 88F6281 Hardware Specifications 8.6 8.6.1 AC Electrical Specifications See Section 8.7, Differential Interface Electrical Characteristics, on page 118 for differential interface specifications. Reference Clock AC Timing Specifications Table 45: Reference Clock AC Timing Specifications D e s c r i p t io n CPU and Core Reference Clock Frequency Clock duty cycle Slew rate Pk-Pk jitter E t h er n e t R e f e r e n c e C lo c k Frequency in MII/MMII-MAC mode FGE_TXCLK_OUT FGE_RXCLK MII/MMII-MAC mode clock duty cycle DCGE_TXCLK_OUT DCGE_RXCLK Slew rate SRGE_TXCLK_OUT SRGE_RXCLK A u d io E x te r na l R e fe r e n c e C lo c k Audio external reference clock S / P D I F R e c o v e r e d M a s t e r C lo c k S/PDIF recovered master clock I S R e f e r e n c e C lo c k I2S clock SP I O ut pu t C l o c k SPI output clock RTC Reference Clock RTC_XIN crystal frequency FRTC_XIN FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FTS0_CLK, FTS1_CLK FEXT_CLK FEXT_CLK 9.61 9.61 9.61 9.61 32.768 kHz 4 FSPI_SCK TCLK/30 TCLK/4 MHz 2 FI2S_BCLK 64 X Fs kHz 3 2 Sy m b o l Min Max Units Notes FREF_CLK_XIN DCREF_CLK_XIN SRREF_CLK_XIN JRREF_CLK_XIN 25 50 ppm 40 0.7 25 + 50 ppm 60 MHz % V/ns 1 200 ps 2.5 100 ppm 35 50 + 100 ppm 65 MHz 7 % 7 0.7 V/ns 1, 7 FAU_EXTCLK 256 X Fs kHz 3 FAU_SPDFRMCLK 256 X Fs kHz 3 Tra n s p o r t St r e a m ( T S ) O u t pu t M o de R e f e r e n ce C l o c k TS output clock in parallel mode TS output clock in serial mode 12.5 83 MHz MHz 5 5 Tr a n s po r t St re a m In p ut M o d e R e fe re n c e C lo c k TS input clock in parallel mode TS input clock in serial mode 13.5 83 MHz MHz Tr a n s p o r t St r e a m E x t e r n a l R e f e r e n c e C lo c k TS external clock in parallel mode TS external clock in serial mode 12.5 83 MHz MHz 5 5 Doc. No. MV-S104859-U0 Rev. E Page 86 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications Table 45: Reference Clock AC Timing Specifications (Continued) D e s c r i p t io n T D M _ S PI O u tp ut C lo c k TDM_SPI output clock S M I M a s t e r M o d e R e f e r e n c e C l o ck SMI output MDC clock T WS I M a s t er M o d e R e fe re n c e C lo c k SCK output clock PT P R e fe r e n c e C lo c k Frequency Clock duty cycle Slew rate Pk-Pk jitter FPTP_CLK DCPTP_CLK SRPTP_CLK JRPTP_CLK 125 100 ppm 40 0.7 100 125 + 100 ppm 60 MHz % V/ns ps 1 FTW_SCK TCLK/ 1600 kHz 6 FGE_MDC TCLK/128 MHz FTDM_SPI_SCK 8.192 MHz Sy m b o l Min Max Units Notes Notes: 1. Slew rate is defined from 20% to 80% of the reference clock signal. 2. For additional information regarding configuring this clock, see the Serial Memory Interface Control Register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. 3. Fs is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the Audio (I2S / S/PDIF) Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). 4. The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components are provided internally. Connect the crystal and the passive network as recommended by the crystal manufacturer. The frequency can be set using the TS Interface Configuration register (see the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications). For the minimum value refer to the Baud Rate Register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications. The Ethernet Reference Clock parameters refer both to the reference clock for an Ethernet port configured using the dedicated port pins and for an Ethernet port configured using the multiplexed port pins. 5. 6. 7. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 87 88F6281 Hardware Specifications 8.6.2 8.6.2.1 SDRAM DDR2 Interface AC Timing SDRAM DDR2 Interface AC Timing Table 400 MHz @ 1.8V Description Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH(avg) tCL(avg) tDSI tDHI tIPW 0.40 0.40 0.35 0.35 0.35 0.34 0.34 -0.11 0.35 0.40 0.48 0.48 -0.42 0.70 0.60 Min 400.0 0.11 0.52 0.52 Max Units MHz ns ns tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) Notes 1 1 - Table 46: SDRAM DDR2 Interface AC Timing Table Clock frequency DQ and DM valid output time before DQS transition DQ and DM valid output time after DQS transition DQ and DM output pulse w idth DQS output high pulse w idth DQS output low pulse w idth DQS falling edge to CLK-CLKn rising edge DQS falling edge from CLK-CLKn rising edge DQS latching rising transitions to associated clock edges DQS w rite preamble DQS w rite postamble Average CLK-CLKn high-level w idth Average CLK-CLKn low -level w idth DQ input setup time relative to DQS in transition DQ input hold time relative to DQS in transition Address and control output pulse w idth Notes: tCK(avg) 1, 2, 3 tCK(avg) 1, 2, 4 ns ns tCK(avg) - General comment: All timing values are defined from Vref to Vref, unless otherw ise specified. General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate defined from Vref +/-125 mV). General comment: tCK(avg) is calculated as the average clock period across any consecutive 200 cycle w indow . General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point. General comment: For Address and Control output timing parameters, refer to the Address Timing table. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. Refer to SDRAM DDR2 clock specifications table for more information. 3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses. 4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses. Doc. No. MV-S104859-U0 Rev. E Page 88 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications Table 47: SDRAM DDR2 Interface Address Timing Table 400 MHz @ 1.8V Description Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Address and Control valid output time before CLK-CLkn rising edge Address and Control valid output time after CLK-CLKn rising edge Sym bol tAOVB tAOVA tAOVB tAOVA Min 0.65 0.65 2.95 0.65 Max Units ns ns ns ns Notes 1, 2 1, 2 1, 3 1, 3 Notes: General comment: All timing values w ere measured from vref to vref, unless otherw ise specified. General comment: For all signals, the load is CL = 14 pF. 1. This timing value is defined on CLK / CLKn crossing point. 2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge. For more information, see register settings. 3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge. and 2T mode is enabled. For more information, see register settings. Except for ODT, CKE and CS signals. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 89 88F6281 Hardware Specifications 8.6.2.2 SDRAM DDR2 Clock Specifications Description Sym bol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty) tCK(abs) tCH(abs) tCL(abs) Min -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 -100 Max 100 80 200 160 150 175 200 200 300 450 100 Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes 1 2 3 4 5 5 5 5 5 5 6 7 8 9 Table 48: SDRAM DDR2 Clock Specifications Clock period jitter Clock perior jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n=6...10, inclusive Cumulative error across n cycles, n=11...50, inclusive Duty cycle jitter Absolute clock period Absolute clock high pulse w idth Absolute clock low pulse w idth See note 7 See note 8 See note 9 Notes: General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified. 1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}. tJIT(per) defines the single period jitter w hen the DLL is already locked. 2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. 3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 - tCKi|. tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked. 4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. 5. tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). Please refer to JEDEC Standard No. 79-2C (DDR2 SDRAM Specification), Chapter 5 (page 100) for more information. 6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here, tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}. 7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max. 8. tCH(abs),min = tCH(avg),min x tCK(avg),min + tJIT(duty),min; tCH(abs),max = tCH(avg),max x tCK(avg),max + tJIT(duty),max. 9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJIT(duty),min; tCL(abs),max = tCL(avg),max x tCK(avg),max + tJIT(duty),max. Doc. No. MV-S104859-U0 Rev. E Page 90 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.2.3 SDRAM DDR2 Interface Test Circuit Figure 5: SDRAM DDR2 Interface Test Circuit VTT Test Point 50 ohm CL 8.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram tDSH CLK CLKn DQS tWPRE DQSn tCH tCL tDSS tDQSH tDQSL tWPST tDIPW DQ tDOVB tDOVA Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 91 88F6281 Hardware Specifications Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram CLK CLKn tCH tCL ADDRESS/ CONTROL tIPW tAOVB tAOVA Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram DQS DQSn DQ tDSI tDHI Doc. No. MV-S104859-U0 Rev. E Page 92 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.3 8.6.3.1 Reduced Gigabit Media Independent Interface (RGMII) AC Timing RGMII AC Timing Table Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V Description Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified. 1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively. 2. For all signals, the load is CL = 5 pF. Sym bol fCK Tskew T Tskew R Tcyc Duty_G Duty_T Min -0.50 1.00 7.20 0.45 0.40 Max 125.0 0.50 2.60 8.80 0.55 0.60 Units Notes MHz ns ns ns tCK tCK 2 1,2 2 2 Table 50: RGMII 10/100 AC Timing Table at 3.3V Description Clock frequency Data to Clock output skew Data to Clock input skew Clock cycle duration Duty cycle for Gigabit Duty cycle for 10/100 Megabit Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. General comment: If the PHY does not support internal-delay mode, the PC board design requires routing clocks so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. For 10/100 Mbps RGMII, the Max value is unspecified. 1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively. 2. For all signals, the load is CL = 5 pF. Sym bol fCK Tskew T Tskew R Tcyc Duty_G Duty_T 1.00 7.20 0.45 0.40 Min 25.0 -0.50 0.50 2.60 8.80 0.55 0.60 Max Units Notes MHz ns ns ns tCK tCK 2 1,2 2 2 Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 93 88F6281 Hardware Specifications 8.6.3.2 RGMII Test Circuit Figure 9: RGMII Test Circuit Test Point CL 8.6.3.3 RGMII AC Timing Diagram Figure 10: RGMII AC Timing Diagram TX CLOCK (At Transmitter) TX DATA TskewT RX CLOCK (At Receiver) RX DATA TskewR Doc. No. MV-S104859-U0 Rev. E Page 94 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.4 8.6.4.1 Gigabit Media Independent Interface (GMII) AC Timing GMII AC Timing Table 125 MHz Description Sym bol tCK tCKrx tHIGH tLOW tR tF tSETUP tHOLD tOVB tOVA Min 7.5 7.5 2.5 2.5 2.0 0.0 2.5 0.5 Max 8.5 1.0 1.0 Units ns ns ns ns ns ns ns ns ns ns Notes 1 1 1, 2 1, 2 1 1 Table 51: GMII AC Timing Table GTX_CLK cycle time RX_CLK cycle time GTX_CLK and RX_CLK high level w idth GTX_CLK and RX_CLK low level w idth GTX_CLK and RX_CLK rise time GTX_CLK and RX_CLK fall time Data input setup time relative to RX_CLK rising edge Data input hold time relative to RX_CLK rising edge Data output valid before GTX_CLK rising edge Data output valid after GTX_CLK rising edge Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max). 8.6.4.2 GMII Test Circuit Figure 11: GMII Test Circuit Test Point CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 95 88F6281 Hardware Specifications 8.6.4.3 GMII AC Timing Diagrams Figure 12: GMII Output AC Timing Diagram tLOW tHIGH VIH(min) GTX_CLK VIL(max) VIH(min) TXD, TX_EN, TX_ER VIL(max) tOVB tOVA Figure 13: GMII Input AC Timing Diagram tLOW tHIGH VIH(min) RX_CLK VIL(max) VIH(min) RXD, RX_EN, RX_ER tSETUP VIL(max) tHOLD Doc. No. MV-S104859-U0 Rev. E Page 96 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.5 8.6.5.1 Media Independent Interface/Marvell Media Independent Interface (MII/MMII) AC Timing MII/MMII MAC Mode AC Timing Table Description Sym bol tSU tHD tOV Min 3.5 2.0 0.0 Max 10.0 Units ns ns ns Notes 1 Table 52: MII/MMII MAC Mode AC Timing Table Data input setup relative to RX_CLK rising edge Data input hold relative to RX_CLK rising edge Data output delay relative to MII_TX_CLK rising edge Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. 1. For all signals, the load is CL = 5 pF. 8.6.5.2 MII/MMII MAC Mode Test Circuit Figure 14: MII/MMII MAC Mode Test Circuit Test Point CL 8.6.5.3 MII/MMII MAC Mode AC Timing Diagrams Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram Vih(min) MII_TX_CLK Vil(max) Vih(min) TXD, TX_EN, TX_ER TOV Vil(max) Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 97 88F6281 Hardware Specifications Figure 16: MII/MMII MAC Mode Input AC Timing Diagram Vih(min) RX_CLK Vih(min) RXD, RX_EN, RX_ER tSU tHD Vil(max) Doc. No. MV-S104859-U0 Rev. E Page 98 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.6 8.6.6.1 Serial Management Interface (SMI) AC Timing SMI Master Mode AC Timing Table Description Sym bol fCK tDC tSU tHO tOVB tOVA Min Max Units MHz tCK ns ns ns ns Notes 2 1 1 Table 53: SMI Master Mode AC Timing Table MDC clock frequency MDC clock duty cycle MDIO input setup time relative to MDC rise time MDIO input hold time relative to MDC rise time MDIO output valid before MDC rise time MDIO output valid after MDC rise time See note 2 0.4 40.0 0.0 15.0 15.0 0.6 - Notes: General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF. 2. See "Reference Clocks" table for more details. 8.6.6.2 SMI Master Mode Test Circuit Figure 17: MDIO Master Mode Test Circuit VDDIO Test Point 2 kilohm MDIO CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 99 88F6281 Hardware Specifications Figure 18: MDC Master Mode Test Circuit Test Point MDC CL 8.6.6.3 SMI Master Mode AC Timing Diagrams Figure 19: SMI Master Mode Output AC Timing Diagram VIH(min) MDC VIH(min) MDIO VIL(max) tOVB tOVA Figure 20: SMI Master Mode Input AC Timing Diagram VIH(min) MDC VIH(min) MDIO VIL(max) tSU tHO Doc. No. MV-S104859-U0 Rev. E Page 100 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.7 8.6.7.1 JTAG Interface AC Timing JTAG Interface AC Timing Table Table 54: JTAG Interface AC Timing Table 30 MHz Description JTClk frequency JTClk minimum pulse w idth JTClk rise/fall slew rate JTRSTn active time TMS, TDI input setup relative to JTClk rising edge TMS, TDI input hold relative to JTClk rising edge JTClk falling edge to TDO output delay Sym bol fCK Tpw Sr/Sf Trst Tsetup Thold Tprop 0.45 0.50 1.0 6.67 13.0 1.0 Min 30.0 0.55 8.33 Max Units MHz tCK V/ns ms ns ns ns Notes 2 1 Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For TDO signal, the load is CL = 10 pF. 2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time. 8.6.7.2 JTAG Interface Test Circuit Figure 21: JTAG Interface Test Circuit Test Point CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 101 88F6281 Hardware Specifications 8.6.7.3 JTAG Interface AC Timing Diagrams Figure 22: JTAG Interface Output Delay AC Timing Diagram Tprop (max) VIH VIL JTCK TDO Tprop (min) Figure 23: JTAG Interface Input AC Timing Diagram JTCK TMS,TDI Tsetup Thold Doc. No. MV-S104859-U0 Rev. E Page 102 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.8 8.6.8.1 Two-Wire Serial Interface (TWSI) AC Timing TWSI AC Timing Table Description Sym bol fCK tLOW tHIGH tSU tHD tr tf tOV Min Max Units kHz tCK tCK ns ns ns ns tCK Notes 1 2 2 2, 3 2, 3 2 Table 55: TWSI Master AC Timing Table SCK clock frequency SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge See note 1 0.47 0.40 250.0 0.0 0.0 1000.0 300.0 0.4 Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max). Table 56: TWSI Slave AC Timing Table 100 kHz Description SCK minimum low level w idth SCK minimum high level w idth SDA input setup time relative to SCK rising edge SDA input hold time relative to SCK falling edge SDA and SCK rise time SDA and SCK fall time SDA output delay relative to SCK falling edge Sym bol tLOW tHIGH tSU tHD tr tf tOV Min 4.7 4.0 250.0 0.0 0.0 Max 1000.0 300.0 4.0 Units us us ns ns ns ns us Notes 1 1 1, 2 1, 2 1 Notes: General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified. 1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm. 2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max). Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 103 88F6281 Hardware Specifications 8.6.8.2 TWSI Test Circuit Figure 24: TWSI Test Circuit VDDIO Test Point RL CL 8.6.8.3 TWSI AC Timing Diagrams Figure 25: TWSI Output Delay AC Timing Diagram tHIGH tLOW Vih(min) SCK Vil(max) Vih(min) SDA tOV(min) Vil(max) tOV(max) Figure 26: TWSI Input AC Timing Diagram tLOW tHIGH Vih(min) SCK Vil(max) Vih(min) SDA Vil(max) tSU tHD Doc. No. MV-S104859-U0 Rev. E Page 104 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.9 8.6.9.1 Sony/Philips Digital Interconnect Format (S/PDIF) AC Timing S/PDIF AC Timing Table Description Sym bol Ftxtol Frxtol Txjit Txjitgain Rxjit Min -50.0 -100.0 Max 50.0 100.0 0.05 3.0 10.0 0.25 0.2 Units ppm ppm UI dB UI UI UI Notes 1 1, 2 3 4 5 6 Table 57: S/PDIF AC Timing Table Output frequency accuracy Input frequency accuracy Output jitter - total peak-to-peak Jitter transfer gain Input jitter - total peak-to-peak - Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications, IEC 60958-3:2003(E), Chapter 7.3, January 2003. 1. For all signals, the load is CL = 10 pF. 2. Using inristic jitter filter. 3. Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003. 4. Defined for up to 5 Hz. 5. Defined from 200 Hz to 400 kHz. 6. Defined for above 400 kHz. Note For additional information about working with a coax connection, see the 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 105 88F6281 Hardware Specifications 8.6.9.2 S/PDIF Test Circuit Figure 27: S/PDIF Test Circuit Test Point CL Doc. No. MV-S104859-U0 Rev. E Page 106 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.10 8.6.10.1 Inter-IC Sound Interface (I2S) AC Timing Inter-IC Sound (I2S) AC Timing Table Description Sym bol fCK tCH/tCL tSU tHO tOD Min Max Units MHz tCK tCK ns tCK Notes 2 1 1 Table 58: Inter-IC Sound (I2S) AC Timing Table I2SBCLK clock frequency I2SBCLK clock high/low level pulse w idth I2SDI input setup time relative to I2SBCLK rise time I2SDI input hold time relative to I2SBCLK rise time I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time See note 2 0.37 0.10 0.00 0.10 0.70 Notes: General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For all signals, the load is CL = 15 pF. 2. See "Reference Clocks" table for more details. 8.6.10.2 Inter-IC Sound (I2S) Test Circuit Figure 28: Inter-IC Sound (I2S) Test Circuit Test Point CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 107 88F6281 Hardware Specifications 8.6.10.3 Inter-IC Sound (I2S) AC Timing Diagrams Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram tCL tCH VIH(min) I2SBCLK VIL(max) VIH(min) I2SDO, I2SLRCLK VIL(max) tODmin tODmax Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram tCL tCH VIH(min) I2SBCLK VIL(max) VIH(min) I2SDI VIL(max) tSU tHO Doc. No. MV-S104859-U0 Rev. E Page 108 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.11 8.6.11.1 Time Division Multiplexing (TDM) Interface AC Timing TDM Interface AC Timing Table 8.192 MHz Description Sym bol 1/tC tDTY tR/tF tD tSU tHD Min 0.256 0.4 0.0 10.0 10.0 Max 8.192 0.6 3.0 20.0 Units MHz tC ns ns ns ns Notes 1, 3 1 1, 2, 8 1, 4, 6 5, 7 5, 7 Table 59: TDM Interface AC Timing Table PCLK cycle time PCLK duty cycle PCLK rise/fall time DTX and FSYNC valid after PCLK rising edge DRX and FSYNC setup time relative to PCLK falling edge DRX and FSYNC hold time relative to PCLK falling edge Notes: General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified. 1. For all signals, the load is CL = 20 pF. 2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform. 3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192 MHz frequencies only. 4. This parameter is relevant to FSYNC signal in master-mode only. 5. This parameter is relevant to FSYNC signal in slave-mode only. 6. In negative-mode, the DTX signal is relative to PCLK falling edge. 7. In negative-mode, the DRX signal is relative to PCLK rising edge. 8. This parameter is relevant w hen the PCLK pin is output. 8.6.11.2 TDM Interface Test Circuit Figure 31: TDM Interface Test Circuit Test Point CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 109 88F6281 Hardware Specifications 8.6.11.3 TDM Interface Timing Diagrams Figure 32: TDM Interface Output Delay AC Timing Diagram tC PCLK DTX tD tD Figure 33: TDM Interface Input Delay AC Timing Diagram tC PCLK DRX tSU tHD Doc. No. MV-S104859-U0 Rev. E Page 110 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.12 8.6.12.1 Serial Peripheral Interface (SPI) AC Timing SPI (Master Mode) AC Timing Table SPI Description Sym bol fCK tCH tCL tSR tDOV tCSB tCSA tSU tHD Min Max Units MHz tCK tCK V/ns ns ns ns tCK ns Notes 3 1 1 1 1 1 1 2 2 Table 60: SPI (Master Mode) AC Timing Table SCLK clock frequency SCLK high time SCLK low time SCLK slew rate Data out valid relative to SCLK falling edge CS active before SCLK rising edge CS not active after SCLK rising edge Data in setup time relative to SCLK rising edge Data in hold time relative to SCLK rising edge See Note 3 0.46 0.46 0.5 -2.5 8.0 8.0 0.2 5.0 2.5 - Notes: General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified. General comment: tCK = 1/fCK. 1. For all signals, the load is CL = 10 pF. 2. Defined from vddio/2 to vddio/2. 3. See "Reference Clocks" table for more details. 8.6.12.2 SPI (Master Mode) Test Circuit Figure 34: SPI (Master Mode) Test Circuit Test Point CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 111 88F6281 Hardware Specifications 8.6.12.3 SPI (Master Mode) Timing Diagrams Figure 35: SPI (Master Mode) Output AC Timing Diagram tCH SCLK tCL Data Out tDOVmin tDOVmax CS tCSB tCSA Figure 36: SPI (Master Mode) Input AC Timing Diagram SCLK Data in tSU tHD Doc. No. MV-S104859-U0 Rev. E Page 112 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.13 8.6.13.1 Secure Digital Input/Output (SDIO) Interface AC Timing Secure Digital Input/Output (SDIO) AC Timing Table Description Symbol fCK tWL/tWH tTLH/tTHL tDOVB tDOVA tISU tIHD Min 0 0.35 6.5 2.5 7.0 0.0 Max 50 3.0 Units MHz tCK ns ns ns ns ns Notes 1, 3 1, 3 2, 3 2, 3 2 2 Table 61: SDIO Host in High Speed Mode AC Timing Table Clock frequency in Data Transfer Mode Clock high/low level pulse w idth Clock rise/fall time CMD, DAT output valid before CLK rising edge CMD, DAT output valid after CLK rising edge CMD, DAT input setup relative to CLK rising edge CMD, DAT input hold relative to CLK rising edge Notes: General comment: tCK = 1/fCK. 1. Defined on VIL(max) and VIH(min) levels. 2. Defined on VDDIO/2 for Clock signal, and VIL(max) / VIH(min) for CMD & DAT signals. 3. For all signals, the load is CL = 10 pF. 8.6.13.2 Secure Digital Input/Output (SDIO) Test Circuit Figure 37: Secure Digital Input/Output (SDIO) Test Circuit VDDIO Test Point 50 KOhm CL Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 113 88F6281 Hardware Specifications 8.6.13.3 Secure Digital Input/Output (SDIO) AC Timing Diagrams Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram tWL tWH VIH(min) CLK VDDIO/2 VIL(max) VIH(min) DAT, CMD VIL(max) tDOVB tDOVA Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram tWL tWH VIH(min) CLK VDDIO/2 VIL(max) VIH(min) DAT, CMD VIL(max) tISU tIHD Doc. No. MV-S104859-U0 Rev. E Page 114 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications 8.6.14 8.6.14.1 Description Clock frequency Transport Stream (TS) Interface AC Timing Transport Stream Interface AC Timing Table Sym bol fCK tLOW tHIGH tOV Min Max Units MHz tCK tCK tCK Notes 1 2 2 2, 3 Table 62: Transport Stream Output Interface AC Timing Table See note 1 0.4 0.4 0.4 0.6 0.6 0.6 Clock minimum low level w idth Clock minimum high level w idth Data output valid after Clock rising edge Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. For all signals, the load is CL = 5 pF. 3. When configured to falling edge, the tOV parameter is relative to Clock falling edge. Table 63: Transport Stream Input Interface AC Timing Table Description Clock frequency Clock minimum low level w idth Clock minimum high level w idth Data input setup time relative to Clock rising edge Data input setup time relative to Clock rising edge Sym bol fCK tLOW tHIGH tSU tHD Min Max Units MHz tCK tCK tCK tCK Notes 1 2 2 See note 1 0.35 0.35 0.30 0.30 0.65 0.65 - Notes: General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified. General comment: tCK = 1/fCK. 1. See "Reference Clocks" table for more details. 2. When configured to falling edge, the tSU/tHD parameters are relative to Clock falling edge. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 115 88F6281 Hardware Specifications 8.6.14.2 Transport Stream Interface Test Circuit Figure 40: Transport Stream Interface Test Circuit Test Point CL 8.6.14.3 Transport Stream Interface Timing Diagrams Figure 41: Transport Stream Output Interface AC Timing Diagram tHIGH tLOW Vih(min) Clock Vil(max) Vih(min) Data Out tOV(min) tOV(max) Vil(max) Doc. No. MV-S104859-U0 Rev. E Page 116 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications AC Electrical Specifications Figure 42: Transport Stream Input Interface AC Timing Diagram tLOW tHIGH Vih(min) Clock Vil(max) Vih(min) Data In Vil(max) tSU tHD Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 117 88F6281 Hardware Specifications 8.7 Differential Interface Electrical Characteristics This section provides the reference clock, AC, and DC characteristics for the following differential interfaces: PCI Express Interface Electrical Characteristics SATA Interface Electrical Characteristics USB Electrical Characteristics 8.7.1 8.7.1.1 Differential Interface Reference Clock Characteristics PCI Express Interface Differential Reference Clock Characteristics Description Sym bol fCK DCrefclk SRrefclk VIHrefclk VILrefclk Vcross Vcrs_dlta Tperavg Tperabs Tccjit 0.4 0.6 150.0 250.0 -300.0 9.8 Min 100.0 0.6 4.0 -150.0 550.0 140.0 2800.0 10.2 150.0 Max Units MHz tCK V/nS mV mV mV mV ppm nS pS Notes 3 1 1 2 - Table 64: PCI Express Interface Differential Reference Clock Characteristics Clock frequency Clock duty cycle Differential rising/falling slew rate Differential high voltage Differential low voltage Absolute crossing point voltage Variation of Vcross over all rising clock edges Average differential clock period accuracy Absolute differential clock period Differential clock cycle-to-cycle jitter Notes: General Comment: The reference clock timings are based on 100 ohm test circuit. General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1, March 2005, section 2.1.3 for more information. 1. Defined on a single-ended signal. 2. Including jitter and spread spectrum. 3. Defined from -150 mV to +150 mV on the differential w aveform. Doc. No. MV-S104859-U0 Rev. E Page 118 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications Differential Interface Electrical Characteristics PCI Express Interface Spread Spectrum Requirements Table 65: PCI Express Interface Spread Spectrum Requirements Sym bol Fmod Fspread Min 0.0 -0.5 Max 33.0 0.0 Units kHz % Notes 1 1 Notes: 1. Defined on linear sw eep or "Hershey's Kiss" (US Patent 5,631,920) modulations. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 119 88F6281 Hardware Specifications 8.7.2 8.7.2.1 PCI Express Interface Electrical Characteristics PCI Express Interface Driver and Receiver Characteristics Description Sym bol BR UI Bppm Driver parameters Table 66: PCI Express Interface Driver and Receiver Characteristics Min 2.5 400.0 -300.0 300.0 Max Units Gbps ps ppm Notes 2 Baud rate Unit interval Baud rate tolerance Differential peak to peak output voltage Minimum TX eye w idth Differential return loss Common mode return loss DC differential TX impedance VTXpp TTXeye TRLdiff TRLcm ZTXdiff Receiver parameters 0.8 0.75 10.0 6.0 80.0 1.2 120.0 V UI dB dB Ohm 1 1 - Differential input peak to peak voltage Minimum receiver eye w idth Differential return loss Common mode return loss DC differential RX impedance DC common input impedance Notes: VRXpp TRXeye RRLdiff RRLcm ZRXdiff ZRXcm 0.175 0.4 10.0 6.0 80.0 40.0 1.2 120.0 60.0 V UI dB dB Ohm Ohm 1 1 - General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005. 1. Defined from 50 MHz to 1.25 GHz. 2. Does not account for SSC dictated variations. Doc. No. MV-S104859-U0 Rev. E Page 120 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications Differential Interface Electrical Characteristics 8.7.2.2 PCI Express Interface Test Circuit Figure 43: PCI Express Interface Test Circuit Test Points + C_TX D+ D- C_TX 50 ohm 50 ohm When measuring Transmitter output parameters, C_TX is an optional portion of the Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF. C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 121 88F6281 Hardware Specifications 8.7.3 SATA Interface Electrical Characteristics The driver and receiver characteristics for the SATA-I Interface Gen1i Mode and the SATA-II Interface Gen2i Mode are provided in the following sections. Doc. No. MV-S104859-U0 Rev. E Page 122 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications Differential Interface Electrical Characteristics 8.7.3.1 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics Description Sym bol BR Bppm Fssc SSCtol UI Driver Parameters Zdifftx Zsetx RLOD RLOD RLOD RLOD RLOD Vdifftx TJ5 DJ5 TJ250 DJ250 Zdiffrx Zsetx RLID RLID RLID RLID RLID RLID Vdiffrx TJ5 DJ5 TJ250 DJ250 Receiver Parameters -350.0 30.0 -5000.0 666.67 85.0 40.0 14.0 8.0 6.0 3.0 1.0 400.0 85.0 40.0 18.0 14.0 10.0 8.0 3.0 1.0 325.0 115.0 600.0 0.355 0.175 0.470 0.220 115.0 600.0 0.430 0.250 0.600 0.350 Min 1.5 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps Ohm Ohm dB dB dB dB dB mV UI UI UI UI Ohm Ohm dB dB dB dB dB dB mV UI UI UI UI Notes 2 1 1 1 1 - Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Output differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Differential impedance Single ended impedance Differential return loss (75 MHz-150 MHz) Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Input differential voltage Total jitter at connector data-data, 5UI Deterministic jitter at connector data-data, 5UI Total jitter at connector data-data, 250UI Deterministic jitter at connector data-data, 250UI Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Total jitter is defined as TJ = (14 * RJ) + DJ w here Rj is random jitter. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 123 88F6281 Hardware Specifications 8.7.3.2 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics Description Sym bol BR Bppm Fssc SSCtol UI Driver Parameters Vdifftx RLOD RLOD RLOD RLOD RLOD TJ10 DJ10 TJ500 DJ500 Receiver Parameters Vdiffrx RLID RLID RLID RLID RLID RLID TJ10 DJ10 TJ500 DJ500 -350.0 30.0 -5000.0 333.33 400.0 14.0 8.0 6.0 3.0 1.0 275.0 18.0 14.0 10.0 8.0 3.0 1.0 700.0 0.30 0.17 0.37 0.19 750.0 0.46 0.35 0.60 0.42 Min 3.0 350.0 33.0 0.0 Max Units Gbps ppm kHz ppm ps mV dB dB dB dB dB UI UI UI UI mV dB dB dB dB dB dB UI UI UI UI Notes 1,2 3 3 4 4 5 3 3 4 4 Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics Baud Rate Baud rate tolerance Spread spectrum modulation frequency Spread spectrum modulation Deviation Unit Interval Output differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Differential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Input differential voltage Differential return loss (150 MHz-300 MHz) Differential return loss (300 MHz-600 MHz) Differential return loss (600 MHz-1.2 GHz) Differential return loss (1.2 GHz-2.4 GHz) Differential return loss (2.4 GHz-3.0 GHz) Differential return loss (3.0 GHz-5.0 GHz) Total jitter at connector clock-data Deterministic jitter at connector clock-data Total jitter at connector clock-data Deterministic jitter at connector clock-data Notes: General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. 0.45-0.55 UI is the range w here the signal meets the minimum level. 2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description for more details. 3. Defined for BR/10. 4. Defined for BR/500. 5. 0.5 UI is the point w here the signal meets the minimum level. Doc. No. MV-S104859-U0 Rev. E Page 124 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications Differential Interface Electrical Characteristics 8.7.4 8.7.4.1 USB Electrical Characteristics USB Driver and Receiver Characteristics Low Speed Description Table 69: USB Low Speed Driver and Receiver Characteristics Sym bol BR Bppm Driver Parameters VOH VOL VCRS TLR TLF TLRFM TUDJ1 TUDJ2 Receiver Parameters VIH VIL VDI Max 1.5 -15000.0 15000.0 2.8 0.0 1.3 75.0 75.0 80.0 -95.0 -150.0 2.0 0.2 3.6 0.3 2.0 300.0 300.0 125.0 95.0 150.0 0.8 Min Units Mbps ppm V V V ns ns % ns ns V V V Notes 1 2 3 3, 4 3, 4 5 5 - Baud Rate Baud rate tolerance Ouput single ended high Ouput single ended low Output signal crossover voltage Data fall time Data rise time Rise and fall time matching Source jitter total: to next transition Source jitter total: for paired transitions Input single ended high Input single ended low Differential input sensitivity Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. See "Data Signal Rise and Fall Time" w aveform. 4. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 5. Including frequency tolerance. Timing difference betw een the differential data signals. Defined at crossover point of differential data signals. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 125 88F6281 Hardware Specifications Table 70: USB Full Speed Driver and Receiver Characteristics Full Speed Sym bol BR Bppm Driver Parameters Ouput single ended high VOH Ouput single ended low VOL Output signal crossover voltage VCRS Output rise time TFR Output fall time TFL Source jitter total: to next transition TDJ1 Source jitter total: for paired transitions TDJ2 Source jitter for differential transition to SE0 transition TFDEOP Receiver Parameters Input single ended high VIH Input single ended low VIL Differential input sensitivity VDI Receiver jitter : to next transition tJR1 Receiver jitter: for paired transitions tJR2 Baud Rate Baud rate tolerance Description Max 12.0 -2500.0 2500.0 2.8 0.0 1.3 4.0 4.0 -3.5 -4.0 -2.0 2.0 0.2 -18.5 -9.0 3.6 0.3 2.0 20.0 20.0 3.5 4.0 5.0 0.8 18.5 9.0 Min Units Mbps ppm V V V ns ns ns ns ns V V V ns ns Notes 1 2 4 3, 4 3, 4 5, 6 5, 6 6 6 6 Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1.. Defined w ith 1.425 kilohm pull-up resistor to 3.6V. 2.. Defined w ith 14.25 kilohm pull-dow n resistor to ground. 3. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 4. See "Data Signal Rise and Fall Time" w aveform. 5. Including frequency tolerance. Timing difference betw een the differential data signals. 6. Defined at crossover point of differential data signals. Doc. No. MV-S104859-U0 Rev. E Page 126 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Electrical Specifications Differential Interface Electrical Characteristics Table 71: USB High Speed Driver and Receiver Characteristics High Speed Description Baud Rate Baud rate tolerance Data signaling high Data signaling low Data rise time Data fall time Data source jitter Differential input signaling levels Data signaling common mode voltage range Receiver jitter tolerance Sym bol BR Bppm Driver Parameters VHSOH VHSOL THSR THSF Receiver Parameters VHSCM See note 3 -50.0 500.0 See note 3 mV 3 3 Max 480.0 -500.0 500.0 360.0 440.0 -10.0 10.0 500.0 500.0 See note 2 Min Units Mbps ppm mV mV ps ps Notes 1 1 2 Notes: General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000. General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified. General Comment: To comply w ith the values presented in this table, refer to your local Marvell representative for register settings. 1. Defined from 10% to 90% for rise time and 90% to 10% for fall time. 2. Source jitter specified by the "TX eye diagram pattern template" figure. 3. Receiver jitter specified by the "RX eye diagram pattern template" figure. 8.7.4.2 USB Interface Driver Waveforms Figure 44: Low/Full Speed Data Signal Rise and Fall Time Rise Time 90% VCRS 10% 10% 90% Fall Time Differential Data Lines TR TF Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 127 88F6281 Hardware Specifications Figure 45: High Speed TX Eye Diagram Pattern Template +525mV +475mV +400mV Differential +300mV 0 Volts Differential -300mV - 400mV Differential -475mV -525mV 7.5% 0% 37.5% 62.5% 92.5% 100% Figure 46: High Speed RX Eye Diagram Pattern Template +525mV +475mV +400mV Differential +175mV 0 Volts Differential -175mV - 400mV Differential -475mV -525mV 12.5% 0% 35 65 87.5% 100% Doc. No. MV-S104859-U0 Rev. E Page 128 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Thermal Data (Preliminary) 9 Thermal Data (Preliminary) Table 72 provides the package thermal data for the device. This data is derived from simulations that were run according to the JEDEC standard. The thermal parameters are preliminary and subject to change. Note TET The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Before designing a system it is recommended to refer to these documents: Application Note, AN-63 Thermal Management for Selected Marvell(R) Products, Document Number MV-S300281-00 White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Document Number MV-S700019-00. Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) Sy m b o l JA JT JC JB D e fin i ti on Ai rf lo w Va lu e ( C / W ) 0[m/s] Thermal resistance: junction to ambient. Thermal characterization parameter: junction to case center. Thermal resistance: junction to case (not air-flow dependent) Thermal characterization parameter: junction to the bottom of the package. Thermal resistance: junction to the bottom of the package (not air-flow dependent) 10.7 20.2 7.0 1 [ m /s ] 18.7 7.0 8.4 10.6 10.9 10.6 2 [ m /s ] 18.1 7.1 JB Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 129 88F6281 Hardware Specifications 10 Package This section provides the 88F6281 package drawing and dimensions. Figure 47: HSBGA 288-pin Package and Dimensions Doc. No. MV-S104859-U0 Rev. E Page 130 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Package Table 73: HSBGA 288-pin Package Dimensions S y m bo l Package Body size X Y X Y D E eD eE A A3 A2 C o m m on Di m e nsi o n ( in m il li m e t e r s ) HSBGA 19.000 19.000 1.000 1.000 1.910 0.190 0.850 ref 0.560 ref 0.600 A1 b X Y M N P Q R S CA aaa bbb ccc ddd eee fff n X Y D1 E1 0.400 ~ 0.600 0.500 ~ 0.700 17.000 17.000 12.000 ~ 13.200 0.100 0.300 0.500 1.215 ref 0.200 0.250 0.350 0.200 0.250 0.100 288 17.000 17.000 Ball pitch Total thickness Mold thickness Substrate thickness Ball diameter Standoff Ball width Mold area H/S exposed size H/S flatness H/S shift with substrate edge H/S shift with mold area Chamfer Package edge tolerance Substrate flatness Mold flatness Copolarity Ball offset (package) Ball offset (ball) Ball count Edge ball center-to-center Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 131 88F6281 Hardware Specifications 11 11.1 Part Order Numbering/Package Marking Part Order Numbering Figure 48 shows the part order numbering scheme for the 88F6281. Refer to Marvell Field Application Engineers (FAEs) or representatives for further information when ordering parts. Figure 48: Sample Part Number 88F6281 -xx-BIA2Cxxx-xxxx Part number 88F6281 Die revision Custom code (optional) Speed code 100 = 1.0 GHz 120 = 1.2 GHz 150 = 1.5 GHz Custom code Temperature code C = Commercial I = Industrial Package code BIA = 288-pin HSBGA Environmental code 2 = Green (RoHS 6/6 and Halogen-free) r Table 74: 88F6281 Part Order Options P a c k a g e Ty p e 288-pin BGA 288-pin BGA 288-pin BGA P a r t O rd e r N u m b e r 88F6281-XX-BIA2C100 (Green, RoHS 6/6 and Halogen-free package), 1.0 GHz 88F6281-xx-BIA2C120 (Green, RoHS 6/6 and Halogen-free package), 1.2 GHz 88F6281-xx-BIA2C150 (Green, RoHS 6/6 and Halogen-free package), 1.5 GHz Doc. No. MV-S104859-U0 Rev. E Page 132 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Part Order Numbering/Package Marking Package Marking 11.2 Package Marking Figure 49 shows a sample Commercial package marking and pin 1 location for the 88F6281. Figure 49: Commercial Package Marking and Pin 1 Location Marvell logo Country of origin code (Contained in the mold ID or marked as the last line on the package.) 88F6-BIAe Lot Number YYWW xx@ Country of Origin 88F6281-xx XXXX Part number prefix, package code, environmental code 88F6 = Part number prefix BIA = Package code e = Environmental code: 2 = Green Part number and die revision code 88F6281 = Part number Date code, custom code, assembly plant code YYWW = Date code (YY = year, WW = Work Week) xx = Custom code @ = Assembly plant code xx = Die revision code Pin 1 location Temperature and speed code C100 = Commercial, 1.0 GHz C120 = Commercial, 1.2 GHz C150 = Commercial, 1.5 GHz Note: The above drawing is not drawn to scale. Location of markings is approximate. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 133 88F6281 Hardware Specifications A Table 75: R e v i s io n E Revision History Revision History D a te December 2, 2008 C o m m e n ts Revision 1. In Figure 1, 88F6281 Pin Logic Diagram, on page 18, changed the GE_TXCLKOUT pin to input/output and added a note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock. 2. In Table 6, PCI Express Interface Pin Assignments, on page 26, revised the description of the PEX_CLK_P/N pins to state that they can be configured as input or output according to the reset strap. 3. In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28, indicated that: * When the GE_TXCLKOUT pin is used as an MII/MMII Transmit Clock, it is an input pin. * When the MPP[29]/GE1[9] pin is used as a GMII Transmit Clock, it is a Tri-State output pin. 4. In Table 12, RTC Interface Pin Assignments, on page 35, changed the type for RTC_XOUT to analog. 5. In the description of signal AU_SPDFRMCLK in Table 17, Audio (S/PDIF / I2S) Interface Signal Assignment, on page 40, added a reference to the new AU_SPDFRMCLK information in the Reference Clock AC Timing Specifications table. 6. In Table 24, Unused Interface Strapping, on page 49, revise the description for configuring the PCI Express clock signals. 7. At the end of Section 4.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 57, added a note stating that all relevant Gigabit Ethernet signals must be implemented. 8. In the Table 32, Reset Configuration, on page 67, revised the configuration function for parameter CPU_CLK to DDR CLK Ratio. 9. In Table 36, Recommended Operating Conditions, on page 77, for parameter RTC_AVDD Analog supply for RTC in Battery Back-up mode, revised the values for the minimum to 1.3V from 1.4V and for the maximum to 1.7V from 1.6V. 10. In Table 37, Thermal Power Dissipation, on page 79: * For the Embedded CPU (VDD_CPU 1.1V) parameter changed the L2 cache frequency to 333 MHz. * for the eFuse during Burning mode parameter added a note: The eFuse burn is done once, and there should be no thermal effect, after it has been burned. 11. In Table 38, Current Consumption, on page 80, for the Embedded CPU (VDD_CPU 1.1V) parameter changed the L2 cache frequency to 333 MHz. 12. * * * * In Table 45, Reference Clock AC Timing Specifications, on page 86: Revised the names of the Ethernet transmit symbols to FGE_TXCLK_OUT, DCGE_TXCLK_OUT, and SRGE_TXCLK_OUT. Added the S/PDIF Recovered Master Clock. Added the Transport Stream External Reference Clock. For the PTP Reference Clock, revised the values for the Frequency, Duty Cycle, and Pk-Pk jitter parameters. 13. In Table 46, SDRAM DDR2 Interface AC Timing Table, on page 88, revised the minimum value for symbol tDHI to 0.70 ns from 0.72 ns. D October 5, 2008 Revision 14. In Table 6, PCI Express Interface Pin Assignments, on page 26, revised the note in the description of the PEX_CLK_P/N pins. 15. In Table 24, Unused Interface Strapping, on page 49, added the eFuse strapping. 16. In Section 6.1.1, Power-Up Sequence Requirements, on page 63 and Section 6.1.2, Power-Down Sequence Requirements, on page 64, added a power up/down requirements for when VHV is in eFuse Burning mode. Doc. No. MV-S104859-U0 Rev. E Page 134 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Revision History Table 75: R e v i s io n Revision History (Continued) D a te C o m m e n ts 17. In Table 36, Recommended Operating Conditions, on page 77: * For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode) and added notes in the comments column for both VHV voltages. * For VDD_M, PEX_AVDD, and USB_AVDD, revised the comments column. * for RTC_AVDD, revised the values for minimum to 1.4V from 1.3V and for maximum to 1.6V from 1.7V. 18. In Table 37, Thermal Power Dissipation, on page 79, revised the row for the SDRAM and added a row for the eFuse. 19. In Table 38, Current Consumption, on page 80, revised the row for the SDRAM and added a row for the eFuse. 20. In Table 45, Reference Clock AC Timing Specifications, on page 86: * For the CPU and Core Reference Clock frequency, revised the values. * For the PTP Reference Clock, added the Slew rate and Pk-Pk jitter parameters. C August 18, 2008 Revision 1. Added the XOR engine to the block diagram in the Product Overview on page 3. 2. Added AN-249: Configuring the Marvell(R) SATA PHY to Transmit Predefined Test Patterns to the list of Related Documentation on page 15. 3. In Figure 1, 88F6281 Pin Logic Diagram, on page 18, added VHV, and MRn and changed PEX_CLK_P/N for input to input/output (I/O). 4. In the pin map and pin list, revised pins F04 to MRn and G04 to VHV. 5. * * * * In Table 3, Power Pin Assignments, on page 21: Added VHV. Changed the voltage for XTAL_AVDD from 2.5V to 1.8V. Changed the voltage for SATA0_AVDD/SATA1_AVDD from 2.5V to 3.3V. Revised the description of VDD_GE_A and VDD_GE_B to add additional information about RGMII. 6. In Table 4, Miscellaneous Pin Assignments, on page 23, added the signal MRn. 7. In Table 5, DDR SDRAM Interface Pin Assignments, on page 24, revised the description of M_NCASL and M_PCAL to indicate the range of the resistor. 8. In Table 6, PCI Express Interface Pin Assignments, on page 26, changed PEX_CLK_P/N for input to input/output (I/O). 9. Added present and active pins to Table 7, SATA Port Interface Pin Assignment, on page 27. 10. In Section 1.2.6, Gigabit Ethernet Port Interface Pin Assignments, on page 28: * Added a note: For the TXCLK, use the GE_RXCLK pin. Also indicated which pins are for port0 and which for port1. * In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28, added a description for MII/MMII to the GE_TXD[3:0], GE_TXCTL, GE_RXCTL, GE_RXCLK, GE_RXD[3:0] rows. Also for pin MPP[30]/GE1[10] added a description for MII/MMII Receive Data Valid. 11. In Table 17, Audio (S/PDIF / I2S) Interface Signal Assignment, on page 40, revised the power rail to VDDO/VDD_GE_B. 12. Revised Table 19, Secure Digital Input/Output (SDIO) Interface Signal Assignment, on page 42 to indicate the pins requiring pull up. 13. Added Table 21, Transport Stream (TS) Interface Signal Assignment, on page 45. 14. Added Section 1.2.20, Precise Timing Protocol (PTP) Interface, on page 47. 15. In Table 23, Internal Pull-up and Pull-down Pins, on page 48, revised the pin numbers and changed pins GE_MDC, MPP[7] and MPP[18] from pull down to pull up and removed MPP[13], MPP[15], and MPP[17] from the table, since they do not require a pull up/down. 16. In Table 2, Unused Interface Strapping, on page 49, revised the description of the strapping for the SATA0_AVDD/SATA1_AVDD pins. Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 135 88F6281 Hardware Specifications Table 75: R e v i s io n 17. * * * * * Revision History (Continued) D a te C o m m e n ts In Section 4.1, Multi-Purpose Pins Functional Summary, on page 51: Changed all references to MPP[0] and MPP[11] from GPI to GPIO. Changed the MPP[6] row in the table to remove the 0x0 option. Added the following bullet at the end of the section, after the tables: When TWSI serial ROM initialization is enabled, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively. Revised the description of SYSRST_OUTn. Added a bullet: Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn). 18. In Table 27, Ethernet Ports Pins Multiplexing, on page 57, added a new configuration option for the Gigabit Ethernet ports: Port 0 MII/MMII, port 1 RGMII. 19. In Section 4.3, TSMP (TS Multiplexing Pins) on MPP, on page 59, added to the description of the TSMP pins. 20. Revised Table 29, 88F6281Clocks, on page 60 and Table 30, Supported Clock Combinations, on page 61. 21. Revised Section 5.1, Spread Spectrum Clock Generator (SSCG), on page 62. 22. In Section 6.2, Hardware Reset, on page 64, added SYSRST_OUTn to the list of pins that are still active during SYSRSTn assertion. 23. Revised Section 6.2.1, Reset Out Signal, on page 65 and Section 6.2.3, SYSRSTn Duration Counter, on page 65 and added Section 6.2.2, Power On Reset (POR), on page 65. 24. In Section 6.3.2, PCI Express Endpoint Reset, on page 66 revised the bulleted items. 25. Revised Section 6.5, Pins Sample Configuration, on page 66. 26. Made major revisions to Table 32, Reset Configuration, on page 67. 27. Revised the first two paragraphs in Section 6.6, Serial ROM Initialization, on page 70. 28. In Section 6.7, Boot Sequence, on page 71 revised the paragraph following step 4. 29. Revised Table 45, Reference Clock AC Timing Specifications, on page 86. 30. In Table 34, IDCODE Register Map, on page 74, revised the description of bits [31:28]. 31. In Table 35, Absolute Maximum Ratings, on page 75: * Added VHV. * Revised the voltage for the SATA and XTAL AVDD parameters. 32. * * * * * 33. * * * * 34. * * * * In the Table 36, Recommended Operating Conditions, on page 77: Added values for VDD_CPU. Added VHV and revised the voltage for the SATA and XTAL AVDD parameters. For the 3.3V interfaces, revised the minimum value to 3.15V and the maximum value to 3.45V (+/-5%). Revised the description of the VDD_GE_A/VDD_GE_B row, to show that RGMII can also operate with a voltage of 3.3V. Revised the values for PEX_AVDD to minimum 1.7V, typical 1.8V, and maximum 1.9V. In Table 37, Thermal Power Dissipation, on page 79 Revised values for Core, Embedded CPU, PCI Express, USB and SATA parameters. Changed all occurrences of VDD_CPU to VDD. Added the row RGMII 3.3V interface. Revised the notes following the table, to remove reference to the trace length or resistance. In Table 38, Current Consumption, on page 80 Revised values for Core, Embedded CPU, SATA, PCI Express and USB parameters. Changed all occurrences of VDD_CPU to VDD. Revised the interface RGMII 1.8V interface to RGMII 1.8V or 3.3V interface. Revised the notes following the table to remove reference to the trace length or resistance. 35. Deleted Section 8.5.2 REF_CLK_XIN 2.5V (CMOS) DC Electrical Specifications and added pin REF_CLK_XIN to Section 8.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 82, since the power rail for the REF_CLK_XIN pin was changed from 2.5V to 1.8V. 36. In Section 8.5.1, General 3.3V (CMOS) DC Electrical Specifications, on page 81, added reference to PTP and RGMII. 37. Revised Table 64, PCI Express Interface Differential Reference Clock Characteristics, on page 118 and Table 65, PCI Express Interface Spread Spectrum Requirements, on page 119. Doc. No. MV-S104859-U0 Rev. E Page 136 Document Classification: Proprietary Information Copyright (c) 2008 Marvell December 2, 2008, Preliminary Revision History Table 75: R e v i s io n Revision History (Continued) D a te C o m m e n ts 38. Revised Figure 25, TWSI Output Delay AC Timing Diagram, on page 104 so that it shows SDA tOV relative to the SCK falling edge, as shown in the two tables that proceed the figure. 39. In Table 73, HSBGA 288-pin Package Dimensions, on page 131, changed the maximum value for the parameter H/S exposed size to 13.200 mm. 40. Revised all of Section 11, Part Order Numbering/Package Marking, on page 132. B April 8, 2008 Revision 1. In the features list: * Added the bullets Precise Timing Protocol (PTP) and Audio Video Bridging networks. * Added the functional block diagram and the usage model diagram. 2. Throughout this specification, LVCMOS and LVTTL were changed to CMOS. 3. In Figure 1, 88F6281 Pin Logic Diagram, on page 18 revised the power pins and removed the interfaces that are multiplexed on the MPP pins. 4. Revised Table 1, Pin Functions and Assignments Table Key, on page 19 to show only terms relevant for this device. 5. In Table 3, Power Pin Assignments, on page 21, added pins SSCG_AVDD and SSCG_AVSS and added the SMI interface at 1.8V and the MII/MMII interface at 3.3V to the description of the interfaces supported by pin VDD_GE_A. 6. In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28, removed pins GE_MDC and GE_MDIO. 7. Added Section 1.2.7, Serial Management Interface (SMI) Interface Pin Assignments, on page 32, with a description of the GE_MDC and GE_MDIO pins. 8. In Table 12, RTC Interface Pin Assignments, on page 35, changed the pin type for RTC_XIN to analog from CMOS. 9. In Table 15, Two-Wire Serial Interface (TWSI) Interface Pin Assignment, on page 38, changed the note to: Requires a pull-up resistor to VDDO. 10. Added Section 2, Unused Interface Strapping, on page 49. 11. In Table 29, 88F6281Clocks, on page 60, revised the description of CPU PLL to mention SSCG. 12. Added Section 5.1, Spread Spectrum Clock Generator (SSCG), on page 62. 13. Added Section 6.1, Power-Up/Down Sequence Requirements, on page 63 and revised the title of Section 6 to reflect this change. 14. In Section 6.4, SheevaTM CPU TAP Controller Reset, on page 66, revised the note referring to sample at reset and added the note: If a signal is pulled up on the board, it must be pulled to the proper voltage level. Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see Table 36, Recommended Operating Conditions, on page 77). 15. In Table 35, Absolute Maximum Ratings, on page 75 and Table 36, Recommended Operating Conditions, on page 77, added the parameter SSCG_VDD. 16. In Table 37, Thermal Power Dissipation, on page 79 added the following: The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design. 17. In Table 38, Current Consumption, on page 80 added the following: The purpose of the Current Consumption table is to support board power design and power module selection. 18. * * * * * In Table 45, Reference Clock AC Timing Specifications, on page 86: Revised the symbols for the Transport Stream (TS) output and input mode reference clocks. Revised the symbols for the SMI master mode reference clock. Revised the symbols for the TWSI master mode reference clock. Revised the description for symbol FRTC_XIN. Removed the RGMII, GMII, MII 100 Mbps, and MII 10 Mbps rows, since they are not relevant to this device. 19. In Table 67, SATA-I Interface Gen1i Mode Driver and Receiver Characteristics, on page 123, added driver and receiver return loss parameters, according to updated standard. A January 28, 2008 Initial release Copyright (c) 2008 Marvell December 2, 2008, Preliminary Document Classification: Proprietary Information Doc. No. MV-S104859-U0 Rev. E Page 137 THIS PAGE IS INTENTIONALLY LEFT BLANK. Contact INFORMATION Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster |
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